Reverse Temperature Dependence of Circuit Performance in High- \kappa/Metal-Gate Technology by Shu-Jen Han, Dechao Guo, Xinlin Wang, Mocuta, A.C., Henson, W.K., Ken Rim

Get full text

Reverse Temperature Dependence of Circuit Performance in High- [Formula Omitted]/Metal-Gate Technology by Han, Shu-Jen, Guo, Dechao, Wang, Xinlin, Mocuta, A.C, Henson, W.K, Rim, Ken

Get full text

Si/sub 1-x-y/Ge x C y -channel p-MOSFET's with improved thermal stability by Mocuta, A.C., Greve, D.W.

Get full text

Si/sub 1-x-y/GexCy-channel p-MOSFET's with improved thermal stability by Mocuta, A.C., Greve, D.W.

Get full text

Si1-x-yGexCy-channel p-MOSFET's with improved thermal stability by Mocuta, A.C, Greve, D.W

Get full text

High Performance 65nm SOI Transistors Using Laser Spike Annealing by Yamashita, T., Fisher, P.A., Gluschenkov, O., Kimura, H., Ramachandran, R., Mocuta, A.C., Kluth, J., Kawamura, T., Onishi, K., Fried, D., Narasimha, S., Brown, D., Sameer Jain, Miyamoto, K., Freeman, G., Deshpande, S.V., Luning, S., Shih-Fen Huang, Pellerin, J., Kuroda, H.

Request full text

Plasma charging damage in SOI technology by Mocuta, A.C., Hook, T.B., Chou, A.I., Wagner, T., Stamper, A.K., Khare, M., Gambino, J.P.

Request full text

Body voltage and history effect sensitivity to key device parameters in 90 nm PD-SOI by Kawanaka, S., Utomo, H., Nii, H., Harifuchi, H., Sudo, G., Rausch, W., Kimura, H., Nakao, T., Park, H., Oh, S.-H., Waite, A., Ketchen, M.B., Womack, S., Narasimha, S., Mocuta, A.C., Ajmera, A., Li, Y., Malik, R., Kohyama, Y., Cheek, J., Yang, I., Clark, W.F., Bhushan, M., Divakaruni, R., Pearson, D.J., Bhasin, R., Mcstay, K., Sherony, M., Fisher, P., Matsumoto, K.

Request full text

High performance CMOS devices on SOI for 90 nm technology enhanced by RSD (raised source/drain) and thermal cycle/spacer engineering by Park, H., Clark, W., Mocuta, A.C., Holt, J., Mo, R., Sato, T., Mocuta, D., Lee, B.H., Dokumaci, O., O'Neil, P., Brown, D., Rausch, W., Suenaga, J., Li, Y., Brown, L., Nakos, J., Hathorn, K., Ronsheim, P., Kimura, H., Doris, B., Sudo, G., Scheer, K., Utomo, H., Mittl, S., Wagner, T., Umebayashi, T., Tsukamoto, M., Kohyama, Y., Cheek, J., Yang, I., Kuroda, H., Toyoshima, Y., Pellerin, J., Matsumoto, K., Schepis, D., Agnello, P., Welser, J., Nii, H., Kawanaka, S., Fisher, P., Oh, S.-H., Snare, J.

Request full text

Gate postdoping to decouple implant/anneal for gate, source/drain, and extension: maximizing polysilicon gate activation for 0.1 /spl mu/m CMOS technologies by Park, H., Schepis, D., Mocuta, A.C., Khare, M., Li, Y., Doris, B., Shukla, S., Hughes, T., Dokumaci, O., Narasimha, S., Fung, S., Snare, J., Lee, B.H., Li, J., Ronsheim, P., Domenicucci, A., Varekamp, P., Ajmera, A., Sleight, J., O'Neil, P., Maciejewski, E., Lavoie, C.

Request full text

High performance sub-40 nm CMOS devices on SOI for the 70 nm technology node by Narasimha, S., Ajmera, A., Park, H., Schepis, D., Zamdmer, N., Jenkins, K.A., Plouchart, J.-O., Lee, W.-H., Mezzapelle, J., Bruley, J., Doris, B., Sleight, J.W., Fung, S.K., Ku, S.H., Mocuta, A.C., Yang, I., Gilbert, P.V., Muller, K.P., Agnello, P., Welser, J.

Request full text

GaN nanocrystals obtained by Ga and N implantations and thermal treatment under N2 into SiO2/Si and SiNx/Si wafers by Aggar, L., Bradai, D., Bourezg, Y.I., Abdesselam, M., Chami, A.C., Mocuta, C., Thiaudiere, D., Speisser, C., Muller, D., Bouillet, C., Le Normand, F.

Get full text