Search Results - Moondanos, J.

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  1. 1
    TRANS: efficient sequential verification of loop-free circuits

    TRANS: efficient sequential verification of loop-free circuits by Khasidashvili, Z., Moondanos, J., Hanna, Z.

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  2. 2
    An enhanced cut-points algorithm in formal equivalence verification

    An enhanced cut-points algorithm in formal equivalence verification by Khasidashvili, Z., Moondanos, J., Kaiss, D., Hanna, Z.

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  3. 3
    Automatic verification of implementations of large circuits against HDL specifications

    Automatic verification of implementations of large circuits against HDL specifications by Hoskote, Y.V., Abraham, J.A., Fussell, D.S., Moondanos, J.

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  4. 4
    Characterization of the worst-case current waveform excitations in general RLC-model power grid analysis

    Characterization of the worst-case current waveform excitations in general RLC-model power grid analysis by Evmorfopoulos, N, Rammou, M, Stamoulis, G, Moondanos, J

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  5. 5
    An Efficient Diagnostic Test Pattern Generation Framework Using Boolean Satisfiability

    An Efficient Diagnostic Test Pattern Generation Framework Using Boolean Satisfiability by Feijun Zheng, Kwang-Ting Cheng, Xiaolang Yan, Moondanos, J., Hanna, Z.

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  6. 6
    JPEG encoding on the Intel MXP5800: a platform-based design case study

    JPEG encoding on the Intel MXP5800: a platform-based design case study by Davare, A., Qi Zhu, Moondanos, J., Sangiovanni-Vincentelli, A.

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  7. 7
    Preserving synchronizing sequences of sequential circuits after retiming

    Preserving synchronizing sequences of sequential circuits after retiming by Mneimneh, M.N., Sakallah, K.A., Moondanos, J.

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  8. 8
    Sequential Redundancy Identification Using Verification Techniques

    Sequential Redundancy Identification Using Verification Techniques by Moondanos, J., Abraham, J.

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  9. 9
    Generation of shorter sequences for high resolution error diagnosis using sequential SAT

    Generation of shorter sequences for high resolution error diagnosis using sequential SAT by Sung-Jui Pan, Kwang-Ting Cheng, Moondanos, J., Hanna, Z.

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  10. 10
    Verification of circuits described in VHDL through extraction of design intent

    Verification of circuits described in VHDL through extraction of design intent by Hoskote, Y.V., Moondanos, J., Abraham, J.A., Fussell, D.S.

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  11. 11
    Abstraction of data path registers for multilevel verification of large circuits

    Abstraction of data path registers for multilevel verification of large circuits by Hoskote, Y.V., Moondanos, J., Abraham, J.A., Fussell, D.S.

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  12. 12
    VERTEX: VERification of Transistor-level circuits based on model EXtraction

    VERTEX: VERification of Transistor-level circuits based on model EXtraction by Moondanos, J., Wehbeh, J.A., Abrahamn, J.A., Saab, D.G.

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