Search Results - Moreira, Matheus Trevisan

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  1. 1
    Optimized Design of an LSSD Scan Cell

    Optimized Design of an LSSD Scan Cell by Rezende Juracy, Leonardo, Trevisan Moreira, Matheus, Kuentzer, Felipe Augusto, de Morais Amory, Alexandre

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  2. 2
    A High-Level Modeling Framework for Estimating Hardware Metrics of CNN Accelerators

    A High-Level Modeling Framework for Estimating Hardware Metrics of CNN Accelerators by Juracy, Leonardo Rezende, Moreira, Matheus Trevisan, de Morais Amory, Alexandre, Hampel, Alexandre F., Moraes, Fernando Gehm

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  3. 3
    A QDI Interconnect for 3D Systems Using Industry Standard EDA and Cell Libraries

    A QDI Interconnect for 3D Systems Using Industry Standard EDA and Cell Libraries by Moreira, Matheus Trevisan, Koven, William, Wu, Tony F., Sumbul, H. Ekin, Beigne, Edith

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  4. 4
    Beware the Dynamic C-Element

    Beware the Dynamic C-Element by Trevisan Moreira, Matheus, Gehm Moraes, Fernando, Vilar Calazans, Ney Laert

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  5. 5
    Voltage scaling on C-elements: A speed, power and energy efficiency analysis

    Voltage scaling on C-elements: A speed, power and energy efficiency analysis by Trevisan Moreira, Matheus, Laert Vilar Calazans, Ney

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  6. 6
    A New CMOS Topology for Low-Voltage Null Convention Logic Gates Design

    A New CMOS Topology for Low-Voltage Null Convention Logic Gates Design by Trevisan Moreira, Matheus, Arendt, Michel Evandro, Aquino Guazzelli, Ricardo, Vilar Calazans, Ney Laert

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  7. 7
    Chronos Link: A QDI Interconnect for Modern SoCs

    Chronos Link: A QDI Interconnect for Modern SoCs by Moreira, Matheus Trevisan, Giaconi, Stefano

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  8. 8
    Read your Circuit: Leveraging Word Embedding to Guide Logic Optimization

    Read your Circuit: Leveraging Word Embedding to Guide Logic Optimization by Neto, Walter Lau, Trevisan Moreira, Matheus, Amaru, Luca, Yu, Cunxi, Gaillardon, Pierre-Emmanuel

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  9. 9
    11.2 A 3D integrated Prototype System-on-Chip for Augmented Reality Applications Using Face-to-Face Wafer Bonded 7nm Logic at <2μm Pitch with up to 40% Energy Reduction at Iso-Area Footprint

    11.2 A 3D integrated Prototype System-on-Chip for Augmented Reality Applications Using Face-to-Face Wafer Bonded 7nm Logic at <2μm Pitch with up to 40% Energy Reduction at Iso-Area... by Wu, Tony F., Liu, Huichu, Sumbul, H. Ekin, Yang, Lita, Baheti, Dipti, Coriell, Jeremy, Koven, William, Krishnan, Anu, Mittal, Mohit, Moreira, Matheus Trevisan, Waugaman, Max, Ye, Laurent, Beigne, Edith

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  10. 10
    Static Differential NCL Gates: Toward Low Power

    Static Differential NCL Gates: Toward Low Power by Moreira, Matheus Trevisan, Arendt, Michel, Moraes, Fernando Gehm, Calazans, Ney Laert Vilar

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  11. 11
    Design of standard-cell libraries for asynchronous circuits with the ASCEnD flow

    Design of standard-cell libraries for asynchronous circuits with the ASCEnD flow by Trevisan Moreira, Matheus, Vilar Calazans, Ney Laert

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  12. 12
    A Survey of Aging Monitors and Reconfiguration Techniques

    A Survey of Aging Monitors and Reconfiguration Techniques by Leonardo Rezende Juracy, Matheus Trevisan Moreira, Alexandre de Morais Amory, Fernando Gehm Moraes

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