Search Results - Morrise, M.

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  1. 1
    Methodological Reconstruction of Historical Seismic Events From Anecdotal Accounts of Destructive Tsunamis: A Case Study for the Great 1852 Banda Arc Mega‐Thrust Earthquake and Tsunami

    Methodological Reconstruction of Historical Seismic Events From Anecdotal Accounts of Destructive Tsunamis: A Case Study for the Great 1852 Banda Arc Mega‐Thrust Earthquake and Tsu... by Ringer, H., Whitehead, J. P., Krometis, J., Harris, R. A., Glatt‐Holtz, N., Giddens, S., Ashcraft, C., Carver, G., Robertson, A., Harward, M., Fullwood, J., Lightheart, K., Hilton, R., Avery, A., Kesler, C., Morrise, M., Klein, M. H.

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  2. 2
    Low-voltage swing logic circuits for a Pentium/spl reg/ 4 processor integer core

    Low-voltage swing logic circuits for a Pentium/spl reg/ 4 processor integer core by Deleganes, D.J., Barany, M., Geannopoulos, G., Kreitzer, K., Morrise, M., Milliron, D., Singh, A.P., Wijeratne, S.

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  3. 3
    Low-voltage swing logic circuits for a Pentium® 4 processor integer core

    Low-voltage swing logic circuits for a Pentium® 4 processor integer core by DELEGANES, Daniel J, BARANY, Micah, GEANNOPOULOS, George, KREITZER, Kurt, MORRISE, Matthew, MILLIRON, Dan, SINGH, Anant P, WIJERATNE, Sapumal

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  4. 4
    Low-voltage swing logic circuits for a Pentium registered 4 processor integer core

    Low-voltage swing logic circuits for a Pentium registered 4 processor integer core by Deleganes, D J, Barany, M, Geannopoulos, G, Kreitzer, K, Morrise, M, Milliron, D, Singh, AP, Wijeratne, S

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    Clocking design automation in Intel's Core i7 and future designs

    Clocking design automation in Intel's Core i7 and future designs by El-Husseini, A. M., Morrise, M.

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  6. 6
    Scalable, sub-1W, sub-10ps clock skew, global clock distribution architecture for Intel® Core™ i7/i5/i3 microprocessors

    Scalable, sub-1W, sub-10ps clock skew, global clock distribution architecture for Intel® Core™ i7/i5/i3 microprocessors by Shamanna, G, Kurd, N, Douglas, J, Morrise, M

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