Search Results - Mudge, T.N.

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  1. 1
    An analytical model for designing memory hierarchies

    An analytical model for designing memory hierarchies by Jacob, B.L., Chen, P.M., Silverman, S.R., Mudge, T.N.

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  2. 2
    Multilevel optimization of pipelined caches

    Multilevel optimization of pipelined caches by Olukotun, K., Mudge, T.N., Brown, R.B.

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  3. 3
    A comment on "An analytical model for designing memory hierarchies"

    A comment on "An analytical model for designing memory hierarchies" by Jacob, B.L., Chen, P.M., Mudge, T.N., Silverman, S.R.

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  4. 4
    Analysis and design of latch-controlled synchronous digital circuits

    Analysis and design of latch-controlled synchronous digital circuits by Sakallah, K.A., Mudge, T.N., Olukotun, O.A.

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  5. 5
    Critical paths in circuits with level-sensitive latches

    Critical paths in circuits with level-sensitive latches by Burks, T.M., Sakallah, K.A., Mudge, T.N.

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  6. 6
    Overview of complementary GaAs technology for high-speed VLSI circuits

    Overview of complementary GaAs technology for high-speed VLSI circuits by Brown, R.B., Bernhardt, B., LaMacchia, M., Abrokwah, J., Parakh, P.N., Basso, T.D., Gold, S.M., Stetson, S., Gauthier, C.R., Foster, D., Crawforth, B., McQuire, T., Sakallah, K., Lomax, R.J., Mudge, T.N.

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  7. 7
    Multiple Bus Architectures

    Multiple Bus Architectures by MUDGE, TREVORN, HAYES, JOHNP, WINSOR, DONALDC

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  8. 8
    Instruction prefetching using branch prediction information

    Instruction prefetching using branch prediction information by I-Cheng K. Chen, Chih-Chieh Lee, Mudge, T.N.

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  9. 9
    Synchronization of pipelines

    Synchronization of pipelines by Sakallah, K.A., Mudge, T.N., Burks, T.M., Davidson, E.S.

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  10. 10
    A complementary GaAs (CGaAs/sup TM/) 32-bit multiply accumulate unit

    A complementary GaAs (CGaAs/sup TM/) 32-bit multiply accumulate unit by Kelley, M.J., Postiff, M.A., Strong, T.D., Brown, R.B., Mudge, T.N.

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  11. 11
    The bi-mode branch predictor

    The bi-mode branch predictor by Chih-Chieh Lee, Chen, I.-C.K., Mudge, T.N.

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  12. 12
    Gallium-arsenide process evaluation based on a RISC microprocessor example

    Gallium-arsenide process evaluation based on a RISC microprocessor example by Brown, R.B., Upton, M., Chandna, A., Huff, T.R., Mudge, T.N., Oettel, R.E.

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  13. 13
    Parallel language constructs for efficient parallel processing

    Parallel language constructs for efficient parallel processing by Clapp, R.M., Mudge, T.N.

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  14. 14
    Translation and execution of distributed Ada programs: Is it still Ada?

    Translation and execution of distributed Ada programs: Is it still Ada? by Volz, R.A., Mudge, T.N., Buzzard, G.D., Krishnan, P.

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  15. 15
    Multilevel optimization in the design of a high-performance GaAs microcomputer

    Multilevel optimization in the design of a high-performance GaAs microcomputer by Olukotun, O.A., Brown, R.B., Lomax, R.J., Mudge, T.N., Sakallah, K.A.

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  16. 16
    Analysis and design of latch-controlled synchronous digital circuits

    Analysis and design of latch-controlled synchronous digital circuits by Sakallah, K.A., Mudge, T.N., Olukotun, O.A.

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  17. 17
    Timing Issues in the Distributed Execution of Ada Programs

    Timing Issues in the Distributed Execution of Ada Programs by Volz, Richard A., Mudge, Trevor N.

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  18. 18
    Analysis of bus hierarchies for multiprocessors

    Analysis of bus hierarchies for multiprocessors by Winsor, D.C., Mudge, T.N.

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  19. 19
    The design of microsupercomputers

    The design of microsupercomputers by Mudge, T.N., Brown, R.B., Birmingham, W.B., Dykstra, J.A., Kayssi, A.I., Lomax, R.J., Olukotun, O.A., Sakallah, K.A., Milano, R.A.

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  20. 20
    The design of a microsupercomputer

    The design of a microsupercomputer by Mudge, T.N., Brown, R.B., Birmingham, W.P., Dykstra, J.A., Kayssi, A.I., Lomax, R.J., Olukotun, O.A., Sakallah, K.A., Milano, R.A.

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