VLSI logic and fault simulation on general-purpose parallel computers by Mueller-Thuns, R.B., Saab, D.G., Damiano, R.F., Abraham, J.A.

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Portable parallel logic and fault simulation by Mueller-Thuns, R.B., Saab, D.G., Damiano, R.F., Abraham, J.A.

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Benchmarking parallel processing platforms: an applications perspective by Mueller-Thuns, R.B., Saab, D.G., Damiano, R.F., Abraham, J.A.

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Automatic generation of behavioral models from switch-level descriptions by Blaauw, D. T., Saab, D. G., Mueller-Thuns, R. B., Abraham, J. A., Rahmeh, J. T.

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SNEL: a switch-level simulator using multiple levels of functional abstraction by Blaauw, D.T., Mueller-Thuns, R.B., Saab, D.G., Banerjee, P., Abraham, J.A.

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CHAMP: concurrent hierarchical and multilevel program for simulation of VLSI circuits by Saab, D.G., Mueller-Thuns, R.B., Blaauw, D., Abraham, J.A., Rahmeh, J.T.

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Design of a scalable parallel switch-level simulator for VLSI by Mueller-Thuns, R.B., Saab, D.G., Abraham, J.A.

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Fault grading of large digital systems by Saab, D.G., Mueller-Thuns, R.B., Blaauw, D., Rahmeh, J.T., Abraham, J.A.

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