Higher radix sparse-2 adders with improved grouping technique by Kumar, V. Chetan, Phaneendra, P. Sai, Ahmed, S. Ershad, Sreehari, V., Muthukrishnan, N. Moorthy, Srinivas, M. B.

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Statistical Parameter-based Automatic Liver Tumor Segmentation from Abdominal CT Scans: A Potiential Radiomic Signature by Kumar, Y. Rakesh, Muthukrishnan, N. Moorthy, Mahajan, Abhishek, Priyanka, P., Padmavathi, G., Nethra, M., Sneha, R., Thakur, Meenakshi H.

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Characterization of titanium etching in Cl2/N2 plasmas by MOORTHY MUTHUKRISHNAN, N, AMBERIADIS, K, ELSHABINI-RIAD, A

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Online battery monitoring using model based approach - impedance by Bayya, Madhuri, Rao, U. M., Prabhakara, B. V. S. S. N., Moorthy Muthukrishnan, N.

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Design of Prefix-Based Optimal Reversible Comparator by Vudadha, C., Phaneendra, P. S., Sreehari, V., Ahmed, S. E., Muthukrishnan, N. M., Srinivas, M. B.

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A Modified Twin Precision Multiplier with 2D Bypassing Technique by Ahmed, S. E., Abraham, S., Veeramanchaneni, S., Moorthy Muthukrishnan, N., Srinivas, M. B.

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Design and Analysis of Reversible Ripple, Prefix and Prefix-Ripple Hybrid Adders by Vudadha, C., Phaneendra, P. S., Ahmed, S. E., Sreehari, V., Muthukrishnan, N. M., Srinivas, M. B.

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Low power, variable resolution pipelined analog to Digital converter with sub flash architecture by Adimulam, Mahesh Kumar, Movva, Krishna Kumar, Veeramachaneni, Sreehari, Muthukrishnan, N Moorthy, Srinivas, M B

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Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs by Vudadha, C., Makkena, G., Nayudu, M. V. S., Phaneendra, P. S., Ahmed, S. E., Veeramachaneni, S., Muthukrishnan, N. M., Srinivas, M. B.

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A Prefix Based Reconfigurable Adder by Chetan Kumar, V., Sai Phaneendra, P., Ershad Ahmed, S., Veeramachaneni, S., Moorthy Muthukrishnan, N., Srinivas, M. B.

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Characterization of Titanium Etching in Cl2 /  N 2 Plasmas by Muthukrishnan, N. Moorthy, Amberiadis, Kostas, Elshabini‐Riad, Aicha

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Design of encoder for ternary logic circuits by Saidutt, P. V., Srinivas, V., Phaneendra, P. S., Muthukrishnan, N. M.

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Conditional sum block for high sparse adders by Phaneendra, P. S., Veeramachaneni, S., Muthukrishnan, N. M., Srinivas, M. B.

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Design of CNFET based ternary comparator using grouping logic by Vudadha, C., Phaneendra P, Sai, Makkena, G., Sreehari, V., Muthukrishnan, N. M., Srinivas, M. B.

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Reconfigurable adders for Binary/BCD addition/subtraction by Ahmed, S. E., Veeramanchaneni, S., Muthukrishnan, N. M., Srinivas, M. B.

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A Novel, Variable Resolution Flash ADC with Sub Flash Architecture by Adimulam, M K, Veeramachaneni, S, Muthukrishnan, N M, Srinivas, M B

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Increment/decrement/2's complement/priority encoder circuit for varying operand lengths by Phaneendra, P. S., Vudadha, C., Ahmed, S. E., Sreehari, V., Muthukrishnan, N. M., Srinivas, M. B.

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A Multiple-Bandwidth 10-bit SAR Analog to Digital Converter by Adimulam, M. K., Movva, K. K., Veeramachaneni, S., Muthukrishnan, N. M., Srinivas, M. B.

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A Reconfigurable INC/DEC/2's Complement/Priority Encoder Circuit with Improved Decision Block by Kumar, V. C., Phaneendra, P. S., Ahmed, S. E., Sreehari, V., Muthukrishnan, N. M., Srinivas, M. B.

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A Unified Architecture for BCD and Binary Adder/Subtractor by Chetan Kumar, V., Sai Phaneendra, P., Ahmed, S. E., Veeramachaneni, S., Moorthy Muthukrishnan, N., Srinivas, M. B.

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