Errors in Projecting Gate Dielectric Reliability From Fowler-Nordheim Stress to Direct-Tunneling Operation by Nicollian, P.E.

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Errors in Projecting Gate Dielectric Reliability From FowleraNordheim Stress to Direct-Tunneling Operation by Nicollian, P E

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Negative bias temperature instability mechanism: The role of molecular hydrogen by Krishnan, Anand T., Chakravarthi, Srinivasan, Nicollian, Paul, Reddy, Vijay, Krishnan, Srikanth

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Device Characteristics and Equivalent Circuits for NMOS Gate-to-Drain Soft and Hard Breakdown in Polysilicon/SiON Gate Stacks by Nicollian, P E, Cakici, R T, Krishnan, A T, Reddy, V K, Seshadri, A

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SPICE simulations of data path timing margins after dielectric breakdown from gate-to-drain using accurate equivalent circuit models by Cakici, R. T., Nicollian, P. E., Chancellor, C. A.

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Gate dielectric reliability in the sub threshold regime by Nicollian, P E, Chancellor, C A, Krishnan, A T

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Impact of gate area on plasma charging damage: the "reverse" antenna effect by Krishnan, A.T., Krishnan, S., Nicollian, P.

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Material dependence of hydrogen diffusion: implications for NBTI degradation by Krishnan, A.T., Chancellor, C., Chakravarthi, S., Nicollian, P.E., Reddy, V., Varghese, A., Khamankar, R.B., Krishnan, S.

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High performance 0.3 mu m CMOS using I-line lithography and BARC by Thakar, G V, Madan, S K, Garza, C M, Krisa, W L, Nicollian, P E, Wise, J L, Lee, C K, McKee, J A, Appel, A T, Esquivel, A L, McNeil, V M, Prinslow, D A, Riemenschneider, B R, Utsumi, T, Eklund, R H, Chapman, R A

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CMOS and interconnect reliability gate dielectric breakdown - modeling and mechanism by Nicollian, P., Eriguchi, K.

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Ultrathin nitrogen-profile engineered gate dielectric films by Hattangady, S.V., Kraft, R., Grider, D.T., Douglas, M.A., Brown, G.A., Tiner, P.A., Kuehne, J.W., Nicollian, P.E., Pas, M.F.

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Low voltage stress-induced-leakage-current in ultrathin gate oxides by Nicollian, P.E., Rodder, M., Grider, D.T., Chen, P., Wallace, R.M., Hattangady, S.V.

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2.5 /spl Omega///spl square/ W/TiN/poly stack gate technology for high density and embedded DRAM technology by Hu, Y., Anderson, D., Rotondaro, A., Obrien, S., Wei-Yung Hsu, Kraft, R., Tiner, P., Nicollian, P., Aur, S.

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60nm gate length dual-Vt CMOS for high performance applications by MEHROTRA, M, WU, J, OLSEN, L, DELOACH, J, MEHIGAN, J, AGARWAL, R, WALSH, S, SEKEL, D, TSUNG, L, VAIDYANATHAN, M, TRENTMAN, B, LIU, K, JAIN, A, AUR, S, KHAMANKAR, R, NICOLLIAN, P, JIANG, Q, XU, Y, CAMPBELL, B, TINER, P, WISE, R, SCOTT, D, RODDER, M, LAAKSONEN, T, KIM, K, BATHER, W, KOSHY, R, CHEN, J, JACOBS, J, UKRAINTSEV, V

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A high performance 90 nm logic technology with a 37 nm gate length, dual plasma nitrided gate dielectric and differential offset spacer by Hornung, B., Bevan, M., Nicollian, P., Chidambaram, P.R., Chakravarthi, S., Gurba, A., Zhang, X., Blatchford, J., Smith, B., Lu, J.P., Deloach, J., Khamankar, R., Rathsack, B., Bowen, C., Thakar, G., Machala, C., Grider, T., Niimi, H., Goodwin, M., Robertson, L., Miles, D., Kirkpatrick, B., AlShareef, H., Varghese, A.

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A 1.2 V, 0.1 /spl mu/m gate length CMOS technology: design and process issues by Rodder, M., Hattangady, S., Yu, N., Shiau, W., Nicollian, P., Laaksonen, T., Chao, C.P., Mehrotra, M., Lee, C., Murtaza, S., Aur, S.

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60 nm gate length dual-Vt CMOS for high performance applications by Mehrotra, M., Wu, J., Jain, A., Laaksonen, T., Kim, K., Bather, W., Koshy, R., Chen, J., Jacobs, J., Ukraintsev, V., Olsen, L., DeLoach, J., Mehigan, J., Agarwal, R., Walsh, S., Sekel, D., Tsung, L., Vaidyanathan, M., Trentman, B., Liu, K., Aur, S., Khamankar, R., Nicollian, P., Jiang, Q., Xu, Y., Campbell, B., Tiner, P., Wise, R., Scott, D., Rodder, M.

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A Shallow-'ikench Isolation Study For 0.18pm Cmos Technology With Emphasis On The Effects Of Well Design, Channel-stop Implants, Trenchl Depth, And Salicide Process by Murtaza, S.S., Chatterjee, A., Mei, P., Amerasekera, A., Nicollian, P., Kittl, J., Breedijk, T., Hanratty, M., Nag, S., Ali, I., Rogers, D., Chen, I.-C.

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Model for the leakage instability in unprogrammed amorphous silicon antifuse devices by Nicollian, P.E., Hunter, W.R.

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Trends for deep submicron VLSI and their implications for reliability by Chatterjee, P.K., Hunter, W.R., Amerasekera, A., Aur, S., Duvvury, C., Nicollian, P.E., Ting, L.M., Ping Yang

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