Search Results - NUN-SIAN TSAI

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  1. 1
    A new and improved structure of polysilicon resistor for subquarter micrometer CMOS device applications

    A new and improved structure of polysilicon resistor for subquarter micrometer CMOS device applications by Thei, Kong-Beng, Cheng, Chung-Long, Lin, Hsin-Chien, Chang, Tong-Sen, Tsai, Nun-Sian, Lee, Kuo-Hwa, Chuang, Hung-Ming, Tsai, Sheng-Fu, Liu, Wen-Chau

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  2. 2
    Underfill characterization for low-k dielectric / Cu interconnect IC flip-chip package reliability

    Underfill characterization for low-k dielectric / Cu interconnect IC flip-chip package reliability by TSAO, Pei-Haw, HUANG, Chender, LII, Mirng-Ji, SU, Bob, TSAI, Nun-Sian

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  3. 3
    Process limitation and device design tradeoffs of self-aligned TiSi2 junction formation in submicrometer CMOS devices

    Process limitation and device design tradeoffs of self-aligned TiSi2 junction formation in submicrometer CMOS devices by CHIH-YUAN LU, JANMYE JAMES SUNG, RUICHEN LIU, NUN-SIAN TSAI, RANBIR SINGH, HILLENIUS, S. J, KIRSCH, H. C

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  4. 4
    Cavity-down thermal-enhanced package reliability evaluation for low-k dielectric / Cu interconnects IC

    Cavity-down thermal-enhanced package reliability evaluation for low-k dielectric / Cu interconnects IC by TSAO, Pei-Haw, HUANG, Chender, LIN, Allan, LII, Mimg-Ji, PERNG, D. J, TSAI, Nun-Sian

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  5. 5
    High-performance salicide shallow-junction CMOS devices for submicrometer VLSI application in twin-tub VI

    High-performance salicide shallow-junction CMOS devices for submicrometer VLSI application in twin-tub VI by Lu, C.-Y., Sung, J.J., Kirsch, H.C., Tsai, N.-S., Liu, R., Manocha, A.S., Hillenius, S.J.

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  6. 6
    An analog/digital BCDMOS technology with dielectric isolation-devices and processes

    An analog/digital BCDMOS technology with dielectric isolation-devices and processes by Lu, C.-Y., Tsai, N.-S., Dunn, C.N., Riffe, P.C., Shibib, M.A., Furnanage, R.A., Goodwin, C.A.

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  7. 7
    A folded extended window MOSFET for ULSI applications

    A folded extended window MOSFET for ULSI applications by Lu, C.-Y., Yaney, D.S., Lee, K.H., Twiford, M.S., Tsai, N.-S., Kook, T., Fritzinger, L.B., Chen, M.-L., Yang, T.S.

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  8. 8
    Design model for minority-carrier well-type guard-rings in CMOS circuits

    Design model for minority-carrier well-type guard-rings in CMOS circuits by Ming-Jer Chen, Chih-Yao Huang, Ping-Nan Tseng, Nun-Sian Tsai, Ching-Yuan Wu

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  9. 9
    A new and improved structure of polysilicon resistor for subquarter micrometer CMOS device applications

    A new and improved structure of polysilicon resistor for subquarter micrometer CMOS device applications by Thei, K, Cheng, Chung-long, Lin, Hsin-chien, Chang, Tong-sen, Tsai, Nun-sian, Lee, Kuo-hwa, Chuang, Hung-ming, Tsai, Sheng-fu, Liu, Wen-chau

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  10. 10
    Overview for 300 mm foundry manufacturing

    Overview for 300 mm foundry manufacturing by Nun-Sian Tsai

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  11. 11
    Bringing a new fab on-line: How TSMC Fab 6 got up and running

    Bringing a new fab on-line: How TSMC Fab 6 got up and running by Tsai, Nun-Sian

    Published in Solid state technology
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  12. 12
    Taking IC manufacturing from 300mm pilot to production

    Taking IC manufacturing from 300mm pilot to production by Tsai, Nun-Sian

    Published in Solid state technology
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  13. 13
    Photoemission identification of emitter resistance for CMOS latch-up hysteresis

    Photoemission identification of emitter resistance for CMOS latch-up hysteresis by Ming-Jer Chen, Jeng-Kuo Jeng, Ping-Nan Tseng, Nun-Sian Tsai, Ching-Yuan Wu

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