Search Results - Naidu K, Jagannadha

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  1. 1
    Adaptive multilevel attention deeplabv3+ with heuristic based frame work for semantic segmentation of aerial images using improved golden jackal optimization algorithm

    Adaptive multilevel attention deeplabv3+ with heuristic based frame work for semantic segmentation of aerial images using improved golden jackal optimization algorithm by P, Anilkumar, P, Venugopal, Kumar S, Satheesh, Naidu K, Jagannadha

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  2. 2
    A 90 % efficiency, 250 MHz on-chip adaptive switched capacitor based DC–DC converter

    A 90 % efficiency, 250 MHz on-chip adaptive switched capacitor based DC–DC converter by Jagannadha Naidu, K., Kittur, Harish M.

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  3. 3
    On Chip DC-DC Converter with High Switching Frequency and Low Ripple Voltage

    On Chip DC-DC Converter with High Switching Frequency and Low Ripple Voltage by Naidu, K. Jagannadha, Kittur, Harish M.

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  4. 4
    Frequency tunable low ripple and fast response on-chip DC–DC converter for DVFS

    Frequency tunable low ripple and fast response on-chip DC–DC converter for DVFS by Naidu, K. Jagannadha, Kittur, Harish M.

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  5. 5
    Design and Verification of Slave Block in Ethernet Management Interface using UVM

    Design and Verification of Slave Block in Ethernet Management Interface using UVM by Naidu, K. Jagannadha, Srikanth, M.

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  6. 6
    Implementation of Delay and Power Monitoring Schemes to Reduce the Power Consumption

    Implementation of Delay and Power Monitoring Schemes to Reduce the Power Consumption by Pavan.T.K., Author, Naidu. K, Jagannadha, V, Nagaraju

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  7. 7
    Partial Reconfigurable Implementation of IEEE802.11g OFDM

    Partial Reconfigurable Implementation of IEEE802.11g OFDM by Sivanantham, S.

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  8. 8
    Partial Reconfigurable Implementation of IEEE802.11g OFDM

    Partial Reconfigurable Implementation of IEEE802.11g OFDM by Sivanantham, S.

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  9. 9
    Implementation of delay and power monitoring schemes to reduce the power consumption

    Implementation of delay and power monitoring schemes to reduce the power consumption by Pavan, T. K., Naidu, K. Jagannadha, Babu, M. Shekar

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  10. 10
    Power reduction using DVFS with a producer-consumer FIFO

    Power reduction using DVFS with a producer-consumer FIFO by Pillamari, Prashanth, Naidu, K. Jagannadha, Kittur, Harish M.

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  11. 11
    An Area and Power Efficient 1-D 4\times 4 Integer DCT Architecture for HEVC

    An Area and Power Efficient 1-D 4\times 4 Integer DCT Architecture for HEVC by Bhaskar, Akshay, Jagannadha Naidu, K

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  12. 12
    Semicustom power gating design

    Semicustom power gating design by Rudraiah, A., Jagannadha Naidu, K., Mallikarjun, Kittur Harish

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