Search Results - Nariani, S.R.

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  1. 1
    A simple wafer-level measurement technique for predicting oxide reliability

    A simple wafer-level measurement technique for predicting oxide reliability by Nariani, S.R., Gabriel, C.T.

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  2. 2
    Amorphous silicon anti-fuse for high-speed FPGA application

    Amorphous silicon anti-fuse for high-speed FPGA application by Jain, V., Nariani, S.R., Gabriel, C., Boardman, W., Chan, D., Chang, K.Y., Gordon, K., Wong, R.

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  3. 3
    An ASIC- Compatible EEPROM Technology

    An ASIC- Compatible EEPROM Technology by Nariani, S.R., Kuang-Yeh Chang, Biegel, M., Kaylor, S., Boardman, W., Chenming Hu

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  4. 4
    Improved reliability of amorphous silicon anti-fuse used in high speed FPGA

    Improved reliability of amorphous silicon anti-fuse used in high speed FPGA by Nariani, S.R., Gabriel, C.T., Jain, V.

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  5. 5
    Internal passivation for suppression of device instabilities induced by backend processes

    Internal passivation for suppression of device instabilities induced by backend processes by Jain, V., Pramanik, D., Nariani, S.R., Hu, C.

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  6. 6
    Gate antenna structures for monitoring oxide quality and reliability

    Gate antenna structures for monitoring oxide quality and reliability by Nariani, S.R., Gabriel, C.T., Pramanik, D., Ng, K.

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  7. 7
    Improved hot carrier reliability of submicron MOS devices by modifying the PECVD IMO film

    Improved hot carrier reliability of submicron MOS devices by modifying the PECVD IMO film by Jain, V., Pramanik, D., Nariani, S.R., Chang, K.Y.

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