Compact thermal modeling of spin transfer torque magnetic tunnel junction by Wang, Y., Cai, H., Naviner, L.A.B., Zhang, Y., Klein, J.O., Zhao, W.S.

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Reliable majority voter based on spin transfer torque magnetic tunnel junction device by Butzen, P.F, Slimani, M, Wang, Y, Cai, H, Naviner, L.A.B

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FIFA: A fault-injection–fault-analysis-based tool for reliability assessment at RTL level by Naviner, L.A.B., Naviner, J.-F., dos Santos, G.G., Marques, E.C., Paiva, N.M.

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CSME: A novel cycle-sensing margin enhancement scheme for high yield STT-MRAM by Cai, H., Liu, M., Zhou, Y., Liu, B., Naviner, L.A.B.

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Compact model of magnetic tunnel junction with stochastic spin transfer torque switching for reliability analyses by Wang, Y., Zhang, Y., Deng, E.Y., Klein, J.O., Naviner, L.A.B., Zhao, W.S.

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A novel BIST for monitoring aging/temperature by self-triggered scheme to improve the reliability of STT-MRAM by Zhou, Y., Cai, H., Zhang, M., Naviner, L.A.B., Yang, J.

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Single-event transient effects on dynamic comparator in 28 nm FDSOI CMOS technology by Maciel, N., Marques, E.C., Naviner, L.A.B., Cai, H.

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Ultra wide voltage range consideration of reliability-aware STT magnetic flip-flop in 28 nm FDSOI technology by Cai, H., Wang, Y., Naviner, L.A.B., Zhao, W.S.

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Ultra wide voltage range consideration of reliability-aware STT magnetic flip-flop in 28nm FDSOI technology by Cai, H., Wang, Y., Naviner, L.A.B., Zhao, W.S.

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A process-variation-resilient methodology of circuit design by using asymmetrical forward body bias in 28nm FDSOI by Wang, Y., Cai, H., Naviner, L.A.B., Zhao, X.X., Zhang, Y., Slimani, M., Klein, J.O., Zhao, W.S.

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A method for efficient implementation of reliable processors by Marques, E C, Naviner, L A B, Naviner, J-F

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A new decoding architecture for algebraic geometry codes by Naviner, L.A.B., Lenz, K.

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Hardware analysis of decoding algorithms for AGC by Belkoura, Z., de Naviner, L.A.B.

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On relevant quality criteria for optimized partitioning methods by De Souza, D.C., De Barros, M.A., Naviner, L.A.B., Neto, B.G.A.

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Architecture for a decoder of algebraic-geometric codes based on Hermitian curves by Lima, L.B.S., Naviner, L.A.B., Jaubert, J., Assis, F.M.

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Efficient computation of logic circuits reliability based on Probabilistic Transfer Matrix by Naviner, L.A.B., de Vasconcelos, M.C.R., Franco, D.T., Naviner, J.-F.

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Fully parametrable downsampler generator by Naviner, L.A.B., Naviner, J.-F., de Barros, M.A.

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