Errors in Projecting Gate Dielectric Reliability From Fowler-Nordheim Stress to Direct-Tunneling Operation by Nicollian, P.E.

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Analytic Extension of the Cell-Based Oxide Breakdown Model to Full Percolation and its Implications by Krishnan, A.T., Nicollian, P.E.

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The Current Understanding of the Trap Generation Mechanisms that Lead to the Power Law Model for Gate Dielectric Breakdown by Nicollian, P.E., Krishnan, A.T., Chancellor, C.A., Khamankar, R.B., Chakravarthi, S., Bowen, C., Reddy, V.K.

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Material dependence of hydrogen diffusion: implications for NBTI degradation by Krishnan, A.T., Chancellor, C., Chakravarthi, S., Nicollian, P.E., Reddy, V., Varghese, A., Khamankar, R.B., Krishnan, S.

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The Traps that cause Breakdown in Deeply Scaled SiON Dielectrics by Nicollian, P.E., Krishnan, A.T., Chancellor, C.A., Khamankar, R.B.

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Experimental evidence for voltage driven breakdown models in ultrathin gate oxides by Nicollian, P.E., Hunter, W.R., Hu, J.C.

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The roles of hydrogen and holes in trap generation and breakdown in ultra-thin SiON dielectrics by Nicollian, P.E., Krishnan, A.T., Bowen, C., Chakravarthi, S., Chancellor, C.A., Khamankar, R.B.

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Low voltage stress-induced-leakage-current in ultrathin gate oxides by Nicollian, P.E., Rodder, M., Grider, D.T., Chen, P., Wallace, R.M., Hattangady, S.V.

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Ultrathin nitrogen-profile engineered gate dielectric films by Hattangady, S.V., Kraft, R., Grider, D.T., Douglas, M.A., Brown, G.A., Tiner, P.A., Kuehne, J.W., Nicollian, P.E., Pas, M.F.

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Model for the leakage instability in unprogrammed amorphous silicon antifuse devices by Nicollian, P.E., Hunter, W.R.

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Extending the reliability scaling limit of SiO/sub 2/ through plasma nitridation by Nicollian, P.E., Baldwin, G.C., Eason, K.N., Grider, D.T., Hattangady, S.V., Hu, J.C., Hunter, W.R., Rodder, M., Rotondaro, A.L.P.

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Trends for deep submicron VLSI and their implications for reliability by Chatterjee, P.K., Hunter, W.R., Amerasekera, A., Aur, S., Duvvury, C., Nicollian, P.E., Ting, L.M., Ping Yang

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High performance 0.3 /spl mu/m CMOS using I-line lithography and BARC by Thakar, G.V., Madan, S.K., Garza, C.M., Krisa, W.L., Nicollian, P.E., Wise, J.L., Lee, C.K., McKee, J.A., Appel, A.T., Esquivel, A.L., McNeil, V.M., Prinslow, D.A., Riemenschneider, B.R., Utsumi, T., Eklund, R.H., Chapman, R.A.

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