Millisecond Anneal and Short-Channel Effect Control in Si CMOS Transistor Performance by Nieh, C.F., Ku, K.C., Chen, C.H., Chang, H., Wang, L.T., Huang, L.P., Sheu, Y.M., Wang, C.C., Lee, T.L., Chen, S.C., Liang, M.S., Gong, J.

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Channel Stress Modulation and Pattern Loading Effect Minimization of Milli-Second Super Anneal for Sub-65nm High Performance SiGe CMOS by Chen, Chien-Hao, Nieh, C.F, Lin, D.W., Ku, K.C., Sheu, J.C., Yu, M.H., Wang, L.T., Lin, H.H., Chang, H.H., Lee, T., Goto, K., Diaz, C., Chen, S.C., Liang, M.S.

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Relaxation-Free Strained SiGe with Super Anneal for 32nm High Performance PMOS and beyond by Yu, M.H., Li, J.H., Lin, H.H., Chen, C.H., Ku, K.C., Nieh, C.F., Hisa, H., Sheu, Y.M., Tsai, C.W., Wang, Y.L., Chu, H.Y., Cheng, H.C., Lee, T.L., Chen, S.C., Liang, M.S.

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A highly scaled, high performance 45 nm bulk logic CMOS technology with 0.242 μm2 SRAM cell by Kuan-Lun Cheng, Wu, C.C., Wang, Y.P., Lin, D.W., Chu, C.M., Tarng, Y.Y., Lu, S.Y., Yang, S.J., Hsieh, M.H., Liu, C.M., Fu, S.P., Chen, J.H., Lin, C.T., Lien, W.Y., Huang, H.Y., Wang, P.W., Lin, H.H., Lee, D.Y., Huang, M.J., Nieh, C.F., Lin, L.T., Chen, C.C., Chang, W., Chiu, Y.H., Wang, M.Y., Yeh, C.H., Chen, F.C., Chang, Y.H., Wang, S.C., Hsieh, H.C., Lei, M.D., Goto, K., Tao, H.J., Cao, M., Tuan, H.C., Diaz, C.H., Mii, Y.J., Wu, C.M.

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