Decreased pregnancy rate is linked to abnormal uterine peristalsis caused by intramural fibroids by Yoshino, O., Hayashi, T., Osuga, Y., Orisaka, M., Asada, H., Okuda, S., Hori, M., Furuya, M., Onuki, H., Sadoshima, Y., Hiroi, H., Fujiwara, T., Kotsuji, F., Yoshimura, Y., Nishii, O., Taketani, Y.

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Practice Guidelines for Primary Care of Acute Abdomen 2015 by Mayumi, Toshihiko, Yoshida, Masahiro, Tazuma, Susumu, Furukawa, Akira, Nishii, Osamu, Shigematsu, Kunihiro, Azuhata, Takeo, Itakura, Atsuo, Kamei, Seiji, Kondo, Hiroshi, Maeda, Shigenobu, Mihara, Hiroshi, Mizooka, Masafumi, Nishidate, Toshihiko, Obara, Hideaki, Sato, Norio, Takayama, Yuichi, Tsujikawa, Tomoyuki, Fujii, Tomoyuki, Miyata, Tetsuro, Maruyama, Izumi, Honda, Hiroshi, Hirata, Koichi

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Evidence for the Presence of Toll-Like Receptor 4 System in the Human Endometrium by Hirata, Tetsuya, Osuga, Yutaka, Hirota, Yasushi, Koga, Kaori, Yoshino, Osamu, Harada, Miyuki, Morimoto, Chieko, Yano, Tetsu, Nishii, Osamu, Tsutsumi, Osamu, Taketani, Yuji

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Possible Pathophysiological Roles of Mitogen-Activated Protein Kinases (MAPKs) in Endometriosis by Yoshino, Osamu, Osuga, Yutaka, Hirota, Yasushi, Koga, Kaori, Hirata, Tetsuya, Harada, Miyuki, Morimoto, Chieko, Yano, Tetsu, Nishii, Osamu, Tsutsumi, Osamu, Taketani, Yuji

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SH4 RISC multimedia microprocessor by Arakawa, F., Nishii, O., Uchiyama, K., Nakagawa, N.

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Characteristic images of deeply infiltrating rectosigmoid endometriosis on transvaginal and transrectal ultrasonography by Koga, Kaori, Osuga, Yutaka, Yano, Tetsu, Momoeda, Mikio, Yoshino, Osamu, Hirota, Yasushi, Kugu, Koji, Nishii, Osamu, Tsutsumi, Osamu, Taketani, Yuji

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An embedded processor core for consumer appliances with 2.8GFLOPS and 36M polygons/s FPU by Arakawa, F., Yoshinaga, T., Hayashi, T., Kiyoshige, Y., Okada, T., Nishibori, M., Hiraoka, T., Ozawa, M., Kodama, T., Irita, T., Kamei, T., Ishikawa, M., Nitta, Y., Nishii, O., Hattori, T.

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A resume-standby application processor for 3G cellular phones by Kamei, T., Ishikawa, M., Hiraoka, T., Irita, T., Abe, M., Saito, Y., Tawara, Y., Ide, H., Furuyama, M., Tamaki, S., Yasu, Y., Shimazaki, Y., Yamaoka, M., Mizuno, H., Irie, N., Nishii, O., Arakawa, F., Hirose, K., Yoshioka, S., Hattori, T.

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An embedded processor core for consumer appliances with 5.6 GFLOPS and 73M polygons/s FPU by Arakawa, Fumio, Okada, Takashi, Hayashi, Tomoichi, Nishii, Osamu, Hattori, Toshihiro

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Design of a second-level cache chip for shared-bus multimicroprocessor systems by Uchiyama, K., Aoki, H., Nishii, O., Hatano, S., Nagashima, O., Oishi, K., Kitano, J.

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A 45nm 37.3GOPS/W heterogeneous multi-core SoC by Yuyama, Y., Ito, M., Kiyoshige, Y., Nitta, Y., Matsui, S., Nishii, O., Hasegawa, A., Ishikawa, M., Yamada, T., Miyakoshi, J., Terada, K., Nojiri, T., Satoh, M., Mizuno, H., Uchiyama, K., Wada, Y., Kimura, K., Kasahara, H., Maejima, H.

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SH-X:an embedded processor core for consumer appliances by Arakawa, F, Ishikawa, M, Kondo, Y, Kamei, T, Ozawa, M, Nishii, O, Hattori, T

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Low-power design of 90-nm SuperH/spl trade/ processor core by Yamada, T., Abe, M., Nitta, Y., Ogura, K., Kusaoke, M., Ishikawa, M., Ozawa, M., Takada, K., Arakawa, F., Nishii, O., Hattori, T.

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On-chip multiple superscalar processors with secondary cache memories by Hanawa, M., Nishimukai, T., Nishii, O., Suzuki, M., Yano, K., Hiraki, M., Shukuri, S., Nishida, T.

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A 200 MHz 1.2 W 1.4 GFLOPS microprocessor with graphic operation unit by Nishii, O., Arakawa, F., Ishibashi, K., Nakano, S., Shimura, T., Suzuki, K., Tachibana, M., Totsuka, Y., Tsunoda, T., Uchiyama, K., Yamada, T., Hattori, T., Maejima, H., Nakagawa, N., Narita, S., Seki, M., Shimazaki, Y., Satomura, R., Takasuga, T., Hasegawa, A.

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Design of a 90nm 4-CPU 4320MIPS SoC with individually managed frequency and 2.4GB/s multi-master on-chip interconnect by Nishii, O., Nonomura, I., Yoshida, Y., Hayase, K., Shibahara, S., Tsujimoto, Y., Takada, M., Hattori, T.

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Performance and power evaluation of SH-X3 multicore system by Takada, M., Shibahara, S., Hayase, K., Kamei, T., Yoshida, Y., Takada, K., Irie, N., Nishii, O., Hattori, T.

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SH by Arakawa, F, Ishikawa, M, Kondo, Y, Kamei, T, Ozawa, M, Nishii, O, Hattori, T

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SH-X: an embedded processor core for consumer appliances by Arakawa, F., Ishikawa, M., Kondo, Y., Kamei, T., Ozawa, M., Nishii, O., Hattori, T.

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A 1000 MIPS BiCMOS microprocessor with superscalar architecture by Nishii, O., Hanawa, M., Nishimukai, T., Suzuki, M., Yano, K., Hiraki, M., Shukuri, S., Nishida, T.

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