High temperature performance and operation of HFETs by Wilson, C.D., O'Neill, A.G., Baier, S.M., Nohava, J.C.

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A self-aligned gate III-V heterostructure FET process for ultrahigh-speed digital and mixed analog/digital LSI/VLSI circuits by Akinwande, A.I., Ruden, P.P., Vold, P.J., Han, C.-J., Grider, D.E., Narum, D.H., Nohava, T.E., Nohava, J.C., Arch, D.K.

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AlGaAs/InGaAs/GaAs quantum well doped channel heterostructure field effect transistors by Ruden, P.P., Shur, M., Akinwande, A.I., Nohava, J.C., Grider, D.E., Baek, J.

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A 500-MHz 1616 complex multiplier using self-aligned gate GaAs heterostructure FET technology by Akinwande, A.I., MacTaggart, I.R., Betz, B.K., Grider, D.E., Lange, T.H., Nohava, J.C., Tetzlaff, D.E., Arch, D.K.

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Delta-doped complementary heterostructure FETs with high Y-value pseudomorphic In/sub 1/Ga/sub 1-y/As channels for ultra-low-power digital IC applications by Grider, D.E., Ruden, P.P., Nohava, J.C., Mactaggart, I.R., Stronczer, J.J., Nohava, T.E., Swirhun, S.S.

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A 4 kbit synchronous static random access memory based upon delta-doped complementary heterostructure insulated gate field effect transistor technology by Grider, D.E., Mactaggart, I.R., Nohava, J.C., Stronczer, J.J., Ruden, P.P., Nohava, T.E., Fulkerson, D., Tetzlaff, D.E.

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Complementary III-V heterostructure FETs for low power integrated circuits by Akinwande, A.I., Ruden, P.P., Grider, D.E., Nohava, J.C., Nohava, T.E., Joslyn, P.D., Breezley, J.E.

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