Transistor aging and reliability in 14nm tri-gate technology by Novak, S., Parker, C., Becher, D., Liu, M., Agostinelli, M., Chahal, M., Packan, P., Nayak, P., Ramey, S., Natarajan, S.

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High sigma measurement of random threshold voltage variation in 14nm Logic FinFET technology by Giles, M. D., Arkali Radhakrishna, N., Becher, D., Kornfeld, A., Maurice, K., Mudanai, S., Natarajan, S., Newman, P., Packan, P., Rakshit, T.

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Analytical Modeling of Output Conductance in Long-Channel Halo-Doped MOSFETs by Mudanai, S., Wei-Kai Shih, Rios, R., Xuemei Xi, Jung-Hoon Rhew, Kuhn, K., Packan, P.

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Self-heat reliability considerations on Intel's 22nm Tri-Gate technology by Prasad, C., Jiang, L., Singh, D., Agostinelli, M., Auth, C., Bai, P., Eiles, T., Hicks, J., Jan, C. H., Mistry, K., Natarajan, S., Niu, B., Packan, P., Pantuso, D., Post, I., Ramey, S., Schmitz, A., Sell, B., Suthram, S., Thomas, J., Tsai, C., Vandervoorn, P.

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An Intel 3 Advanced FinFET Platform Technology for High Performance Computing and SOC Product Applications by Hafez, W., Abdelkader, M., An, S., Auth, C., Bahr, D., Bambery, R., Beck, M., Bhowmick, S., Biggs-houck, J., Caselli, D., Chang, H.-Y., Chang, Y., Chauhan, S., Chikkadi, K., Chu, T., Connor, C., Diana, D., Dong, Y., Elfick, P., Elko-hansen, T., Gala, D., Geppert, C., Govindaraju, S., Grimm, W., Grunes, H., Guler, L., Guo, Z., Gupta, A., Havelia, S., Hazra, J., Islam, A., Jain, A., Jamil, M., Jang, M., Kabir, M., Kameswaran, J., Karl, E., Kelgeri, S., Kennedy, A., Kim, J., Kim, Y., Krishnan, D., Lee, G., Lee, H.-P., Lin, H., Luk, A., Luo, Y., Macfarlane, P., Mamun, A., Marla, K., Mckenna, E., Miah, A., Mistry, K., Mleczko, M., Moon, S., Nardi, D., Natarajan, S., Nolph, C., Nugroho, C., Nyhus, P., Oni, A., Packan, P., Paliwal, A., Pandey, R., Paredes, I., Park, K., Paulson, L., Pierre, A., Plekhanov, P., Prasad, C., Ramaswamy, R., Rode, J., Russell, R., Ryu, S., Saavedra, H., Salisbury, T., Sandford, J., Shah, F., Shang, K., Shekhar, P., Shu, A., Skoug, E., Sohn, J., Song, J., Sprinkle, M., Su, J., Tsao, R., Vaidya, A., Wallace, C., Wang, X., Wang, H., Ward, C., Wickramaratne, S., Wills, M., Wu, T., Xia-hua, Z., Xu, S., Yaung, J., Yu, Y., Zilm, M.

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Bias temperature instability variation on SiON/Poly, HK/MG and trigate architectures by Prasad, C., Agostinelli, M., Hicks, J., Ramey, S., Auth, C., Mistry, K., Natarajan, S., Packan, P., Post, I., Bodapati, S., Giles, M., Gupta, S., Mudanai, S., Kuhn, K.

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Temperature and time dependence of B and P diffusion in Si during surface oxidation by PACKAN, P. A, PLUMMER, J. D

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Reliability characterization of 32nm high-K and Metal-Gate logic transistor technology by Sangwoo Pae, Ashok, Ashwin, Jingyoo Choi, Ghani, T, Jun He, Seok-hee Lee, Lemay, K, Liu, M, Lu, R, Packan, P, Parker, C, Purser, R, St. Amour, Anthony, Woolery, B

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Introductory Remarks: Process Development and Modeling by Goesele, U., Packan, P.

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Linear versus saturated drive current: tradeoffs in super steep retrograde well engineering by Thompson, S E, Packan, P A, Bohr, M T

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High performance Hi-K + metal gate strain enhanced transistors on (110) silicon by Packan, P., Cea, S., Deshpande, H., Ghani, T., Giles, M., Golonzka, O., Hattendorf, M., Kotlyar, R., Kuhn, K., Murthy, A., Ranade, P., Shifren, L., Weber, C., Zawadzki, K.

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Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors by Ghani, T., Mistry, K., Packan, P., Thompson, S., Stettler, M., Tyagi, S., Bohr, M.

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Doping and damage dose dependence of implant induced transient enhanced diffusion below the amorphization threshold by Griffin, P. B., Lever, R. F., Packan, P. A., Plummer, J. D.

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Transient diffusion of low-concentration B in Si due to 29Si implantation damage by PACKAN, P. A, PLUMMER, J. D

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Emitter-base breakdown: Measurement and simulation by Bergner, W., Packan, P., Seidl, B., Klose, H.

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An efficient surface potential solution algorithm for compact MOSFET models by Rios, R., Mudanai, S., Wei-Kai Shih, Packan, P.

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Scaling Transistors into the Deep-Submicron Regime by Packan, Paul A.

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A 65nm ultra low power logic platform technology using uni-axial strained silicon transistors by Jan, C.-H., Bai, P., Choi, J., Curello, G., Jacobs, S., Jeong, J., Johnson, K., Jones, D., Klopcic, S., Lin, J., Lindert, N., Lio, A., Natarajan, S., Neirynck, J., Packan, P., Park, J., Post, I., Patel, M., Ramey, S., Reese, P., Rockford, L., Roskowski, A., Sacks, G., Turkot, B., Wang, Y., Wei, L., Yip, J., Young, I., Zhang, K., Zhang, Y., Bohr, M., Holt, B.

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A three-transistor threshold voltage model for halo processes by Rios, R., Wei-Kai Shih, Shah, A., Mudanai, S., Packan, P., Sandford, T., Mistry, K.

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A high performance 180 nm generation logic technology by Yang, S., Ahmed, S., Arcot, B., Arghavani, R., Bai, P., Chambers, S., Charvat, P., Cotner, R., Gasser, R., Ghani, T., Hussein, M., Jan, C., Kardas, C., Maiz, J., McGregor, P., McIntyre, B., Nguyen, P., Packan, P., Post, I., Sivakumar, S., Steigerwald, J., Taylor, M., Tufts, B., Tyagi, S., Bohr, M.

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