Runtime Task Scheduling for FPGA-Based Embedded Systems Using Just-in-Time Bitstream Prefetching by Duhamel, Alexis, Pillement, Sebastien

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Energy-Efficient GPS Synchronization for Wireless Nodes by Pallier, David, Le Cam, Vincent, Pillement, Sebastien

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A Study in Specification and Hardware Runtime Verification of Critical Embedded Software by Solet, Dimitry, Bechennec, Jean-Luc, Briday, Mikael, Faucou, Sebastien, Pillement, Sebastien

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FTUC: A Flooding Tree Uneven Clustering Protocol for a Wireless Sensor Network by He, Wei, Pillement, Sebastien, Xu, Du

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0–1 ILP-based run-time hierarchical energy optimization for heterogeneous cluster-based multi/many-core systems by Yang, Simei, Le Nours, Sébastien, Mendez Real, Maria, Pillement, Sébastien

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A Measurement-Based Message-Level Timing Prediction Approach for Data-Dependent SDFGs on Tile-Based Heterogeneous MPSoCs by Stemmer, Ralf, Vu, Hai-Dang, Le Nours, Sébastien, Grüttner, Kim, Pillement, Sébastien, Nebel, Wolfgang

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Cooperative Spectrum Sensing with Small Sample Size in Cognitive Wireless Sensor Networks by Men, Shaoyang, Chargé, Pascal, Pillement, Sébastien

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Low-overhead fault-tolerance technique for a dynamically reconfigurable softcore processor by Hung-Manh Pham, Pillement, S., Piestrak, S. J.

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OCEAN, a flexible adaptive Network-On-Chip for dynamic applications by Devaux, Ludovic, Pillement, Sebastien

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FPGA Side Channel Attacks without Physical Access by Ramesh, Chethan, Patil, Shivukumar B., Dhanuskodi, Siva Nishok, Provelengios, George, Pillement, Sebastien, Holcomb, Daniel, Tessier, Russell

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Cluster based MPSoC architecture: an on-chip message passing implementation by Brillu, Romain, Pillement, Sébastien, Lemonnier, Fabrice, Millet, Philippe

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Real-time scheduling on heterogeneous system-on-chip architectures using an optimised artificial neural network by Chillet, Daniel, Eiche, Antoine, Pillement, Sébastien, Sentieys, Olivier

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Designing Efficient Codecs for Bus-Invert Berger Code for Fully Asymmetric Communication by Piestrak, Stanisław J, Pillement, Sebastien, Sentieys, Olivier

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Fault-aware configurable logic block for reliable reconfigurable FPGAs by Basha, B. Chagun, Pillement, Sebastien, Piestrak, Stanislaw J.

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Comments on "A Low-Power Dependable Berger Code for Fully Asymmetric Communication" by Piestrak, S J, Pillement, S, Sentieys, O

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UPaRC: ultra-fast power-aware reconfiguration controller by Bonamy, Robin, Pham, Hung-Manh, Pillement, Sébastien, Chillet, Daniel

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Flexible Interconnection Network for Dynamically and Partially Reconfigurable Architectures by Devaux, Ludovic, Ben Sassi, Sana, Pillement, Sébastien, Chillet, Daniel, Demigny, Didier

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DART: A Functional-Level Reconfigurable Architecture for High Energy Efficiency by Pillement, Sébastien, Sentieys, Olivier, David, Raphaël

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Towards Malicious Exploitation of Energy Management Mechanisms by NOUBIR, Safouane, MENDEZ REAL, Maria, PILLEMENT, Sebastien

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Formal Verification of Integer Dividers:Division by a Constant by Yasin, Atif, Su, Tiankai, Pillement, Sebastien, Ciesielski, Maciej

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