Search Results - Pable, S. D.

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  1. 1
    Ultra-low-power signaling challenges for subthreshold global interconnects

    Ultra-low-power signaling challenges for subthreshold global interconnects by Pable, S.D., Hasan, Mohd

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  2. 2
    A novel robust FPGA routing switch box design for ultra low power applications

    A novel robust FPGA routing switch box design for ultra low power applications by Pable, S.D., Hasan, Mohd

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  3. 3
    Optimization and Characterization of CMOS for Ultra Low Power Applications

    Optimization and Characterization of CMOS for Ultra Low Power Applications by Alam, M. Shah, Hasan, Mohd, Pable, S. D., Kafeel, Mohd. Ajmal

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  4. 4
    Ultra low power DG FinFET based voltage controlled oscillator circuits

    Ultra low power DG FinFET based voltage controlled oscillator circuits by Walunj, R. A., Pable, S. D., Kharate, G. K.

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  5. 5
    Robustness Comparison of Emerging Devices for Portable Applications

    Robustness Comparison of Emerging Devices for Portable Applications by Hasan, Mohd, Kureshi, A. K., Kafeel, Mohd. Ajmal, Pable, S. D.

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  6. 6
    Performance Analysis of CNFET based Interconnect Drivers for Sub-threshold Circuits

    Performance Analysis of CNFET based Interconnect Drivers for Sub-threshold Circuits by Chopade, S S, Pable, S D, Padole, Dinesh V

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  7. 7
    High speed interconnect through device optimization for subthreshold FPGA

    High speed interconnect through device optimization for subthreshold FPGA by Pable, S.D., Hasan, Mohd

    Published in Microelectronics
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  8. 8
    Interconnect Design for Subthreshold Circuits

    Interconnect Design for Subthreshold Circuits by Pable, S. D., Hasan, M.

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  9. 9
    Design considerations and optimisation of clock circuit for ultra-low power sub-threshold applications

    Design considerations and optimisation of clock circuit for ultra-low power sub-threshold applications by Walunj, R. A., Pable, S. D., Kharate, G. K.

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  10. 10
    Interconnect optimization to enhance the performance of subthreshold circuits

    Interconnect optimization to enhance the performance of subthreshold circuits by Pable, S.D., Hasan, Mohd, Abbasi, S.A., Alamoud, A.R.M.

    Published in Microelectronics
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  11. 11
    Design and Analysis of Robust Dual Threshold CMOS Full Adder Circuit in 32nm Technology

    Design and Analysis of Robust Dual Threshold CMOS Full Adder Circuit in 32nm Technology by Islam, A, Akram, M W, Pable, S D, Hasan, M

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  12. 12
    Performance optimization of CNFET based subthreshold circuits

    Performance optimization of CNFET based subthreshold circuits by Pable, S D, Imran, A, Hasan, M

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  13. 13
    A comparative study of CMOS & CNFET based current conveyor at 32nm technology node

    A comparative study of CMOS & CNFET based current conveyor at 32nm technology node by Imran, A, Pable, S D, Hasan, M

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  14. 14
    Performance optimization of LUT of subthreshold FPGA in deep submicron

    Performance optimization of LUT of subthreshold FPGA in deep submicron by Pable, S D, Imran, A, Hasan, M, Islam, A

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  15. 15
    High performance optimized CNFET based current conveyor at 32nm technology node

    High performance optimized CNFET based current conveyor at 32nm technology node by Imran, A, Hasan, M, Pable, S D, Akram, M W

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  16. 16
    A hybrid CMOS-CNFET, 1.4-V 6.8-ppm/°C bandgap reference circuit

    A hybrid CMOS-CNFET, 1.4-V 6.8-ppm/°C bandgap reference circuit by Rahane, Sandip B., Kureshi, A. K., Pable, S. D.

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  17. 17
    A hybrid CMOS-CNFET, 1.4-V 6.8-ppm/ degree C bandgap reference circuit

    A hybrid CMOS-CNFET, 1.4-V 6.8-ppm/ degree C bandgap reference circuit by Rahane, Sandip B, Kureshi, A K, Pable, S D

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  18. 18
    Implementation of a novel co-design of LVTSCR for effective ESD protection in ultra-deep submicron IC

    Implementation of a novel co-design of LVTSCR for effective ESD protection in ultra-deep submicron IC by Kadu, A. U., Turkane, S. M., Pable, S. D., Kureshi, A. K.

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  19. 19
    Performance Analysis of Ultra Low-Power Mixed CNT Interconnects for Scaled Technology

    Performance Analysis of Ultra Low-Power Mixed CNT Interconnects for Scaled Technology by Pable, S. D., Hasan, M., Kafeel, M. A.

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  20. 20
    Optimized design of hybrid CMOS and CNFET 32 nm dual-X current conveyor

    Optimized design of hybrid CMOS and CNFET 32 nm dual-X current conveyor by Imran, A., Pable, S. D., Islam, A., Hasan, M.

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