Search Results - Pacheco-Bautista, Daniel

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  1. 1
    Hybrid Pipeline Hardware Architecture Based on Error Detection and Correction for AES

    Hybrid Pipeline Hardware Architecture Based on Error Detection and Correction for AES by Algredo-Badillo, Ignacio, Ramírez-Gutiérrez, Kelsey A., Morales-Rosales, Luis Alberto, Pacheco Bautista, Daniel, Feregrino-Uribe, Claudia

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  2. 2
    Diseño de un controlador de carga de tres etapas para sistemas fotovoltaicos usando lógica difusa

    Diseño de un controlador de carga de tres etapas para sistemas fotovoltaicos usando lógica difusa by Bautista, Daniel Pacheco, Rito, Elsa Cortés, Acevedo, Francisco Aguilar

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  3. 3
    A fully integral, differential, high-speed, low-power consumption CMOS recovery clock circuit

    A fully integral, differential, high-speed, low-power consumption CMOS recovery clock circuit by Pacheco Bautista, Daniel, Castillo Soria, Francisco Rubén, Linares Aranda, Mónico, Salim Maza, Manuel

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    Diseño de un controlador de carga de tres etapas para sistemas fotovoltaicos usando lógica difusa

    Diseño de un controlador de carga de tres etapas para sistemas fotovoltaicos usando lógica difusa by Pacheco Bautista, Daniel, Cortés Rito, Elsa, Aguilar Acevedo, Francisco

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  5. 5
    Real time FPGA-ANN architecture for outdoor obstacle detection focused in road safety

    Real time FPGA-ANN architecture for outdoor obstacle detection focused in road safety by Algredo-Badillo, Ignacio, Morales-Rosales, Luis Alberto, Hernandez-Gracidas, Carlos Arturo, Cruz-Victoria, Juan Crescenciano, Pacheco-Bautista, Daniel, Morales-Sandoval, Miguel

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  6. 6
    Circuito de recuperación de reloj CMOS completamente integrable, diferencial, de alta velocidad y bajo consumo de potencia

    Circuito de recuperación de reloj CMOS completamente integrable, diferencial, de alta velocidad y bajo consumo de potencia by Pacheco Bautista, Daniel, Castillo Soria, Francisco Rubén, Linares Aranda, Mónico, Salim Maza, Manuel

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    Circuito de recuperación de reloj CMOS completamenteintegrable, diferencial, de alta velocidad y bajo consumode potencia

    Circuito de recuperación de reloj CMOS completamenteintegrable, diferencial, de alta velocidad y bajo consumode potencia by Daniel Pacheco Bautista, Francisco Rubén Castillo Soria, Mónico Linares Aranda, Manuel Salim Maza

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  8. 8
    An Experimental Comparison of Clock Distribution Networks for Systems on Chip

    An Experimental Comparison of Clock Distribution Networks for Systems on Chip by Aranda, M.L., Maza, M.S., Bautista, D.P.

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