Search Results - Panda, P.R.

Refine Results
  1. 1
    Memory allocation and mapping in high-level synthesis - an integrated approach

    Memory allocation and mapping in high-level synthesis - an integrated approach by Jaewon Seo, Taewhan Kim, Panda, P.R.

    Get full text
    Items that this one cites
    Items that cite this one
    Article
    Save to List
    Saved in:
  2. 2
    Low-power memory mapping through reducing address bus activity

    Low-power memory mapping through reducing address bus activity by Panda, P.R., Dutt, N.D.

    Get full text
    Items that this one cites
    Items that cite this one
    Article
    Save to List
    Saved in:
  3. 3
    Augmenting loop tiling with data alignment for improved cache performance

    Augmenting loop tiling with data alignment for improved cache performance by Panda, P.R., Nakamura, H., Dutt, N.D., Nicolau, A.

    Get full text
    Items that this one cites
    Items that cite this one
    Article
    Save to List
    Saved in:
  4. 4
    Front-End Design Flows for Systems on Chip: An Embedded Tutorial

    Front-End Design Flows for Systems on Chip: An Embedded Tutorial by Kumar, A., Panda, P.R.

    Request full text
    Conference Proceeding
    Save to List
    Saved in:
  5. 5
    Online cache state dumping for processor debug

    Online cache state dumping for processor debug by Vishnoi, Anant, Panda, Preeti Ranjan, Balakrishnan, M.

    Request full text
    Conference Proceeding
    Save to List
    Saved in:
  6. 6
    Cache aware compression for processor debug support

    Cache aware compression for processor debug support by Vishnoi, A., Panda, P.R., Balakrishnan, M.

    Request full text
    Conference Proceeding
    Save to List
    Saved in:
  7. 7
    A generic platform for estimation of multi-threaded program performance on heterogeneous multiprocessors

    A generic platform for estimation of multi-threaded program performance on heterogeneous multiprocessors by Sahu, A., Balakrishnan, M., Panda, P.R.

    Request full text
    Conference Proceeding
    Save to List
    Saved in:
  8. 8
    Customization of Register File Banking Architecture for Low Power

    Customization of Register File Banking Architecture for Low Power by Nalluri, R., Garg, R., Panda, P.R.

    Request full text
    Conference Proceeding
    Save to List
    Saved in:
  9. 9
    Local memory exploration and optimization in embedded systems

    Local memory exploration and optimization in embedded systems by Panda, P.R., Dutt, N.D., Nicolau, A.

    Get full text
    Items that this one cites
    Items that cite this one
    Article
    Save to List
    Saved in:
  10. 10
    Power Reduction in VLIW Processor with Compiler Driven Bypass Network

    Power Reduction in VLIW Processor with Compiler Driven Bypass Network by Goel, N., Kumar, A., Panda, P.R.

    Request full text
    Conference Proceeding
    Save to List
    Saved in:
  11. 11
    An integrated algorithm for memory allocation and assignment in high-level synthesis

    An integrated algorithm for memory allocation and assignment in high-level synthesis by Jaewon Seo, Taewhan Kim, Panda, P.R.

    Request full text
    Conference Proceeding
    Save to List
    Saved in:
  12. 12
    Rapid estimation of control delay from high-level specifications

    Rapid estimation of control delay from high-level specifications by Gupta, Gagan Raj, Gupta, Madhur, Panda, Preeti Ranjan

    Request full text
    Conference Proceeding
    Save to List
    Saved in:
  13. 13
    Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures

    Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures by Gangwar, Anup, Balakrishnan, M., Panda, Preeti R., Kumar, Anshul

    Request full text
    Conference Proceeding
    Save to List
    Saved in:
  14. 14
    Memory bank customization and assignment in behavioral synthesis

    Memory bank customization and assignment in behavioral synthesis by Panda, P.R.

    Request full text
    Conference Proceeding
    Save to List
    Saved in:
  15. 15
    Abridged addressing: a low power memory addressing strategy

    Abridged addressing: a low power memory addressing strategy by Panda, P.R.

    Request full text
    Conference Proceeding
    Save to List
    Saved in:
  16. 16
    Specification and design of multi-million gate SOCs

    Specification and design of multi-million gate SOCs by Chandra, R., Henkel, J., Panda, P.R., Parameswaran, S., Ramachandran, L.

    Request full text
    Conference Proceeding
    Save to List
    Saved in:
  17. 17
    SystemC: a modeling platform supporting multiple design abstractions

    SystemC: a modeling platform supporting multiple design abstractions by Panda, Preeti Ranjan

    Request full text
    Items that cite this one
    Conference Proceeding
    Save to List
    Saved in:
  18. 18
    Data cache sizing for embedded processor applications

    Data cache sizing for embedded processor applications by Panda, P.R., Nicolau, N.D., Nicolau, A.

    Request full text
    Conference Proceeding
    Save to List
    Saved in:
  19. 19
    Efficient utilization of scratch-pad memory in embedded processor applications

    Efficient utilization of scratch-pad memory in embedded processor applications by Panda, P.R., Dutt, N.D., Nicolau, A.

    Request full text
    Conference Proceeding
    Save to List
    Saved in:
  20. 20
    Behavioral array mapping into multiport memories targeting low power

    Behavioral array mapping into multiport memories targeting low power by Panda, P.R., Dutt, N.D.

    Request full text
    Conference Proceeding
    Save to List
    Saved in:

Search Tools: