Search Results - Pandini, D.

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  1. 1
    Global and local congestion optimization in technology mapping

    Global and local congestion optimization in technology mapping by Pandini, D., Pileggi, L.T., Strojwas, A.J.

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  2. 2
    Effects of Photobiomodulation Therapy Combined with Static Magnetic Field in Severe COVID-19 Patients Requiring Intubation: A Pragmatic Randomized Placebo-Controlled Trial

    Effects of Photobiomodulation Therapy Combined with Static Magnetic Field in Severe COVID-19 Patients Requiring Intubation: A Pragmatic Randomized Placebo-Controlled Trial by Marchi, Thiago De, Francio, Fabiano, Ferlito, Joao Vitor, Weigert, Renata, Oliveira, Cristiane De, Merlo, Ana Paula, Pandini, Delcio Luis, Junior, Bolivar Antonio Pasqual, Giovanella, Daniela, Tomazoni, Shaiane Silva, Junior, Ernesto Cesar Leal

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  3. 3
    Design solutions for the interconnection parasitic effects in deep sub-micron technologies

    Design solutions for the interconnection parasitic effects in deep sub-micron technologies by Baldi, L., Franzini, B., Pandini, D., Zafalon, R.

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  4. 4
    Modeling the Non-Linear Behavior of Library Cells for an Accurate Static Noise Analysis

    Modeling the Non-Linear Behavior of Library Cells for an Accurate Static Noise Analysis by Forzan, Cristiano, Pandini, Davide

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  5. 5
    Optimum CMOS stack generation with analog constraints

    Optimum CMOS stack generation with analog constraints by Malavasi, E., Pandini, D.

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  6. 6
    Congestion-aware logic synthesis

    Congestion-aware logic synthesis by Pandini, D., Pileggi, L.T., Strojwas, A.J.

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  7. 7
    Design methodologies and architecture solutions for high-performance interconnects

    Design methodologies and architecture solutions for high-performance interconnects by Pandini, D., Forzan, C., Baldi, L.

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  8. 8
    Understanding and modeling the impact of analog IPs on System-on-Chip's EMI

    Understanding and modeling the impact of analog IPs on System-on-Chip's EMI by Forzan, C., Valente, P., Kumar, A., Pandini, D.

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  9. 9
    Why we need statistical static timing analysis

    Why we need statistical static timing analysis by Forzan, C., Pandini, D.

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  10. 10
    A fully-automated desynchronization flow for synchronous circuits

    A fully-automated desynchronization flow for synchronous circuits by Andrikos, Nikolaos, Lavagno, Luciano, Pandini, Davide, Sotiriou, Christos P.

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  11. 11
    EMC-aware design on a microcontroller for automotive applications

    EMC-aware design on a microcontroller for automotive applications by Doriol, P.J., Villavicencio, Y., Forzan, C., Rotigni, M., Graziosi, G., Pandini, D.

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  12. 12
    An ultra-low energy asynchronous processor for wireless sensor networks

    An ultra-low energy asynchronous processor for wireless sensor networks by Necchi, L., Lavagno, L., Pandini, D., Vanzago, L.

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  13. 13
    Including Power Supply Variations into Static Timing Analysis: Methodology and Flow

    Including Power Supply Variations into Static Timing Analysis: Methodology and Flow by Graziano, M., Forzan, C., Pandini, D.

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  14. 14
    Simultaneous Placement and Module Optimization of Analog IC's

    Simultaneous Placement and Module Optimization of Analog IC's by Charbon, E., Malavasi, E., Pandini, D., Sangiovanni-Vincentelli, A.

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  15. 15
    Innovative Design Platforms for Reliable SoCs in Advanced Nanometer Technologies

    Innovative Design Platforms for Reliable SoCs in Advanced Nanometer Technologies by Pandini, D.

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  16. 16
    Evaluating regularity extraction in logic synthesis

    Evaluating regularity extraction in logic synthesis by Chakraborty, A., Macii, A., Macii, E., Poncino, M., Pandini, D.

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  17. 17
    Design solutions for the interconnection parasitic effects in deep sub-micron technologies

    Design solutions for the interconnection parasitic effects in deep sub-micron technologies by Baldi, L, Pranzim, B, Pandini, D, Zafalon, R

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  18. 18
    Reduced order macromodel of coupled interconnects for timing and functional verification of sub-half-micron IC designs

    Reduced order macromodel of coupled interconnects for timing and functional verification of sub-half-micron IC designs by Pandini, D., Scandelara, P., Guardiani, C.

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  19. 19
    A moment matching based methodology for crosstalk analysis

    A moment matching based methodology for crosstalk analysis by Pandini, D., Guardiani, C., Gubian, P.

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  20. 20
    Nonlinear macromodels of large coupled interconnect networks

    Nonlinear macromodels of large coupled interconnect networks by Franzini, B., Forzan, C., Pandini, D., Liu, Y., Guardiani, C.

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