Search Results - Pawlak, Bartek J.

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    Advanced FinFET Devices for Sub-32nm Technology Nodes: Characteristics and Integration Challenges

    Advanced FinFET Devices for Sub-32nm Technology Nodes: Characteristics and Integration Challenges by Veloso, Anabela, Collaert, Nadine, De Keersgieter, An, Witters, Liesbeth, Rooyackers, Rita, Van Dal, Mark J., Duffy, Ray, Pawlak, Bartek J., Lander, Rob J., Hoffmann, Thomas, Biesemans, Serge, Jurczak, Malgorzata

    Published in ECS transactions
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    Simple power-loss analysis method for high-efficiency Interdigitated Back Contact (IBC) silicon solar cells

    Simple power-loss analysis method for high-efficiency Interdigitated Back Contact (IBC) silicon solar cells by Verlinden, Pierre J., Aleman, Monica, Posthuma, Niels, Fernandez, Jara, Pawlak, Bartek, Robbelein, Jo, Debucquoy, Maarteen, Van Wichelen, Koen, Poortmans, Jef

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    Material Aspects and Challenges for SOI FinFET Integration

    Material Aspects and Challenges for SOI FinFET Integration by Van Dal, Mark J., Vellianitis, Georgios, Duffy, Ray, Doornbos, Gerben, Pawlak, Bartek, Duriez, Blandine, Lai, Lhi-Shue, Hikavyy, Andriy Y., Vandeweyer, Tom, Demand, Marc, Altamirano, Efrain, Rooyackers, Rita, Witters, Liesbeth, Collaert, Nadine, Jurczak, Malgorzata, Kaiser, Monja, Weemaes, Robbert G., Lander, Rob

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