Replacement metal gate extendible to 11 nm technology by Yoshida, N., Xinyu Fu, Kun Xu, Yu Lei, Haichun Yang, Shiyu Sun, Hao Chen, Darlak, A., Donohoe, R., Lazik, C., Jakkaraju, R., Noori, A., Hung, S., Peidous, I., Chorng-Ping Chang, Brand, A.

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Sidewall Dislocations in Embedded SiGe Source/Drain Areas of MOSFETs and Their Impact on the Device Performance by Kammler, Thorsten, Peidous, Igor, Wei, Andy, Reichel, Carsten, Heinemann, Stefan, Romero, Karla, Engelmann, Hans-Juergen

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Experimental study of Si3N4 viscosity for calibration of stress-dependent models of silicon oxidation by LOIKO, K. V, PEIDOUS, I. V, YUE ZU, HO, H.-M

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Active corner engineering in the process integration for shallow trench isolation by Balasubramanian, N., Johnson, E., Peidous, I. V., Ming-Jr, Shiu, Sundaresan, R.

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Experimental study and simulation of stress-induced cavities in silicon by LOIKO, K. V, PEIDOUS, I. V, FRENSLEY, W. R

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Implementation of Robust Nickel Alloy Salicide Process for High-Performance 65nm SOI CMOS Manufacturing by Strane, J., Brown, D., Lavoie, C., Suenaga, J., Haran, B., Press, P., Besser, P., Flaitz, P., Gribelyuk, M., Kammler, T., Peidous, I., Huajie Chen, Waidmann, S., Frye, A., DeHaven, P., Domenicucci, A., Murray, C., Knarr, R., Engelmann, H.J., Streck, C., Kahlert, V., Deshpande, S., Leobandung, E., Pellerin, J., Jagannathan, J.

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High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL by Lee, W.-H., Waite, A., Nii, H., Nayfeh, H.M., McGahay, V., Nakayama, H., Fried, D., Chen, H., Black, L., Bolam, R., Cheng, J., Chidambarrao, D., Christiansen, C., Cullinan-Scholl, M., Davies, D.R., Domenicucci, A., Fisher, P., Fitzsimmons, J., Gill, J., Gribelyuk, M., Harmon, D., Holt, J., Ida, K., Kiene, M., Kluth, J., Labelle, C., Madan, A., Malone, K., McLaughlin, P.V., Minami, M., Mocuta, D., Murphy, R., Muzzy, C., Newport, M., Panda, S., Peidous, I., Sakamoto, A., Sato, T., Sudo, G., VanMeer, H., Yamashita, T., Zhu, H., Agnello, P., Bronner, G., Freeman, G., Huang, S.-F., Ivers, T., Luning, S., Miyamoto, K., Nye, H., Pellerin, J., Rim, K., Schepis, D., Spooner, T., Chen, X., Khare, M., Horstmann, M., Wei, A., Kammler, T., Hontschel, J., Bierstedt, H., Engelmann, H.-J., Hellmich, A., Hempel, K., Koerner, G., Neu, A., Otterbach, R., Reichel, C., Trentsch, M., Press, P., Frohberg, K., Schaller, M., Salz, H., Hohage, J., Ruelke, H., Klais, J., Raab, M., Greenlaw, D., Kepler, N.

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SOI and Bulk FinFET Alternatives from the Perspective of Strain Engineering by Peidous, Igor V, Lottes, Charles, Jost, Christopher

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The Effect of Silicide Processing on Stress Reduction in Silicon Device Structures with Strained SiGe Elements by Peidous, Igor, Press, Patrick

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Experimental Study of Si3 N 4 Viscosity for Calibration of Stress‐Dependent Models of Silicon Oxidation by Loiko, Konstantin V., Peidous, Igor V., Zu, Yue, Ho, Hok‐Min

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Methodology for ULSI LOCOS isolation built-in reliability analysis by Loiko, K.V., Peidous, I.V., Hok-Min Ho, Quek, E.K.B., Lim, D.H.Y.

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