Oscillatory Neural Networks Based on TMO Nano-Oscillators and Multi-Level RRAM Cells by Jackson, Thomas C., Sharma, Abhishek A., Bain, James A., Weldon, Jeffrey A., Pileggi, Lawrence

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Exploiting Combinatorial Redundancy for Offset Calibration in Flash ADCs by Keskin, G., Proesel, J., Plouchart, Jean-Olivier, Pileggi, L.

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A Convex Method of Generalized State Estimation Using Circuit-Theoretic Node-Breaker Model by Li, Shimiao, Pandey, Amritanshu, Pileggi, Lawrence

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Asymptotic Probability Extraction for Nonnormal Performance Distributions by Xin Li, Le, J., Gopalakrishnan, P., Pileggi, L.T.

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Two-stage homotopy method to incorporate discrete control variables into AC-OPF by McNamara, Timothy, Pandey, Amritanshu, Agarwal, Aayushya, Pileggi, Lawrence

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Analysis and Background Self-Calibration of Comparator Offset in Loop-Unrolled SAR ADCs by Liu, Shaolong, Rabuske, Taimur, Paramesh, Jeyanandh, Pileggi, Lawrence, Fernandes, Jorge

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Model order-reduction of RC(L) interconnect including variational analysis by Liu, Ying, Pileggi, Lawrence T, Strojwas, Andrzej J

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Quantifying the Efficacy of Logic Locking Methods by Sweeney, Joseph, Garg, Deepali, Pileggi, Lawrence

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Calculating worst-case gate delays due to dominant capacitance coupling by Dartu, Florentin, Pileggi, Lawrence T

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STAC: statistical timing analysis with correlation by Le, Jiayong, Li, Xin, Pileggi, Lawrence T.

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Projection-based statistical analysis of full-chip leakage power with non-log-normal distributions by Li, Xin, Le, Jiayong, Pileggi, Lawrence T.

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TACO: timing analysis with coupling by Arunachalam, Ravishankar, Rajagopal, Karthik, Pileggi, Lawrence T

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Impact of interconnect variations on the clock skew of a gigahertz microprocessor by Liu, Ying, Nassif, Sani R, Pileggi, Lawrence T, Strojwas, Andrzej J

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Inductance 101: modeling and extraction by Beattie, Michael W., Pileggi, Lawrence T.

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The Elmore delay as a bound for RC trees with generalized input signals by Gupta, R., Tutuianu, B., Pileggi, L.T.

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Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS by Calhoun, Benton H., Cao, Yu, Li, Xin, Mai, Ken, Pileggi, Lawrence T., Rutenbar, Rob A., Shepard, Kenneth L.

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A 69.5 mW 20 GS/s 6b Time-Interleaved ADC With Embedded Time-to-Digital Calibration in 32 nm CMOS SOI by Chen, Vanessa H.-C, Pileggi, Lawrence

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A 0.6-to-1V inverter-based 5-bit flash ADC in 90nm digital CMOS by Proesel, J.E., Pileggi, L.T.

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Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction by Li, Peng, Liu, Frank, Li, Xin, Pileggi, Lawrence T., Nassif, Sani R.

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PRIMA: passive reduced-order interconnect macromodeling algorithm by Odabasioglu, A., Celik, M., Pileggi, L.T.

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