Search Results - Pilo, H

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  1. 1
    An SRAM Design in 65-nm Technology Node Featuring Read and Write-Assist Circuits to Expand Operating Voltage

    An SRAM Design in 65-nm Technology Node Featuring Read and Write-Assist Circuits to Expand Operating Voltage by Pilo, H., Barwin, C., Braceras, G., Browning, C., Lamphier, S., Towler, F.

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  2. 2
    A 64Mb SRAM in 22nm SOI technology featuring fine-granularity power gating and low-energy power-supply-partition techniques for 37% leakage reduction

    A 64Mb SRAM in 22nm SOI technology featuring fine-granularity power gating and low-energy power-supply-partition techniques for 37% leakage reduction by Pilo, H., Adams, C. A., Arsovski, I., Houle, R. M., Lamphier, S. M., Lee, M. M., Pavlik, F. M., Sambatur, S. N., Seferagic, A., Wu, R., Younus, M. I.

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  3. 3
    An 8 Mb SRAM in 45 nm SOI Featuring a Two-Stage Sensing Scheme and Dynamic Power Management

    An 8 Mb SRAM in 45 nm SOI Featuring a Two-Stage Sensing Scheme and Dynamic Power Management by Ramadurai, V., Pilo, H., Andersen, J., Braceras, G., Gabric, J., Geise, D., Lamphier, S., Yue Tan

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  4. 4
    A 5.6-ns random cycle 144-Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface

    A 5.6-ns random cycle 144-Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface by Pilo, H., Anand, D., Barth, J., Burns, S., Corson, P., Covino, J., Lamphier, S.

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  5. 5
    A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements

    A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements by Pilo, H., Arsovski, I., Batson, K., Braceras, G., Gabric, J., Houle, R., Lamphier, S., Radens, C., Seferagic, A.

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  6. 6
    An 833-MHz 1.5-W 18-Mb CMOS SRAM with 1.67 Gb/s/pin

    An 833-MHz 1.5-W 18-Mb CMOS SRAM with 1.67 Gb/s/pin by Pilo, H., Allen, A., Covino, J., Hansen, P.R., Lamphier, S., Murphy, C., Traver, T., Yee, P.

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  7. 7
    A 64Mb SRAM in 32nm High-k metal-gate SOI technology with 0.7V operation enabled by stability, write-ability and read-ability enhancements

    A 64Mb SRAM in 32nm High-k metal-gate SOI technology with 0.7V operation enabled by stability, write-ability and read-ability enhancements by Pilo, H, Arsovski, I, Batson, K, Braceras, G, Gabric, J, Houle, R, Lamphier, S, Pavlik, F, Seferagic, A, Liang-Yu Chen, Shang-Bin Ko, Radens, C

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  8. 8
    An 833MHz 1.5W 18Mb CMOS SRAM with 1.67Gb/s/pin

    An 833MHz 1.5W 18Mb CMOS SRAM with 1.67Gb/s/pin by Pilo, H, Allen, A, Covino, J, Hansen, P, Lamphier, S, Murphy, C, Traver, T, Yee, P

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  9. 9
    Bitline contacts in high density SRAMs: design for testability and stressability

    Bitline contacts in high density SRAMs: design for testability and stressability by Pilo, H., Adams, R.D., Busch, R.E., Nelson, E.A., Rudgers, G.E.

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  10. 10
    A 550ps Access-Time Compilable SRAM in 65nm CMOS Technology

    A 550ps Access-Time Compilable SRAM in 65nm CMOS Technology by Wissel, L., Pilo, H., LeBlanc, C., Xiaopeng Wang, Lamphier, S., Fragano, M.

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  11. 11
    Design-for-test methods for stand-alone SRAMS at 1Gb/s/pin and beyond

    Design-for-test methods for stand-alone SRAMS at 1Gb/s/pin and beyond by Pilo, Harold, Hansen, Patrick, Lamphier, Steve, Murphy, Chris

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  12. 12
    An SRAM Design in 65nm and 45nm Technology Nodes Featuring Read and Write-Assist Circuits to Expand Operating Voltage

    An SRAM Design in 65nm and 45nm Technology Nodes Featuring Read and Write-Assist Circuits to Expand Operating Voltage by Pilo, H., Barwin, J., Braceras, G., Browning, C., Burns, S., Gabric, J., Lamphier, S., Miller, M., Roberts, A., Towler, F.

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  13. 13
    A 5.6 ns random cycle 144 Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface

    A 5.6 ns random cycle 144 Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface by Pilo, H., Anand, D., Barth, J., Burns, S., Corson, P., Covino, J., Houghton, R., Lamphier, S.

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  14. 14
    Design-for-test methods for stand-alone SRAMs at 1 Gb/s/pin and beyond

    Design-for-test methods for stand-alone SRAMs at 1 Gb/s/pin and beyond by Pilo, H., Hall, S., Hansen, P., Lamphier, S., Murphy, C.

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  15. 15
    An 833 MHz 1.5 W 18 Mb CMOS SRAM with 1.67 Gb/s/pin

    An 833 MHz 1.5 W 18 Mb CMOS SRAM with 1.67 Gb/s/pin by Pilo, H., Allen, A., Covino, J., Hansen, P., Lamphier, S., Murphy, C., Traver, T., Yee, P.

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  16. 16
    A 300 MHz, 3.3 V 1 Mb SRAM fabricated in a 0.5 /spl mu/m CMOS process

    A 300 MHz, 3.3 V 1 Mb SRAM fabricated in a 0.5 /spl mu/m CMOS process by Pilo, H., Lamphier, S., Towler, F., Hee, R.

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  17. 17
    Embedded memories for the future

    Embedded memories for the future

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  18. 18
    Surface-Enhanced Raman Scattering Plasmonic Enhancement Using DNA Origami-Based Complex Metallic Nanostructures

    Surface-Enhanced Raman Scattering Plasmonic Enhancement Using DNA Origami-Based Complex Metallic Nanostructures by Pilo-Pais, M, Watson, A, Demers, S, LaBean, T. H, Finkelstein, G

    Published in Nano letters
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  19. 19
    Connecting the Nanodots: Programmable Nanofabrication of Fused Metal Shapes on DNA Templates

    Connecting the Nanodots: Programmable Nanofabrication of Fused Metal Shapes on DNA Templates by Pilo-Pais, M, Goldberg, S, Samano, E, LaBean, T. H, Finkelstein, G

    Published in Nano letters
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  20. 20
    ACCESS-OM2 v1.0: a global ocean–sea ice model at three resolutions

    ACCESS-OM2 v1.0: a global ocean–sea ice model at three resolutions by Kiss, Andrew E, Hogg, Andrew McC, Hannah, Nicholas, Dias, Fabio Boeira, Brassington, Gary B, Chamberlain, Matthew A, Chapman, Christopher, Dobrohotoff, Peter, Domingues, Catia M, Duran, Earl R, England, Matthew H, Fiedler, Russell, Griffies, Stephen M, Heerdegen, Aidan, Heil, Petra, Holmes, Ryan M, Klocker, Andreas, Marsland, Simon J, Morrison, Adele K, Munroe, James, Nikurashin, Maxim, Oke, Peter R, Pilo, Gabriela S, Richet, Océane, Abhishek Savita, Spence, Paul, Stewart, Kial D, Ward, Marshall L, Wu, Fanghua, Zhang, Xihan

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