Search Results - Pocek, M

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  1. 1
    Multifocal leucoencephalopathy induced by levamisole

    Multifocal leucoencephalopathy induced by levamisole by Lucia, Piernatale, Pocek, Marco, Passacantando, Anna, Sebastiani, Maria Luisa, De Martinis, Carlo

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  2. 2
    Palliative treatment of neoplastic strictures by self-expanding nitinol Strecker stent

    Palliative treatment of neoplastic strictures by self-expanding nitinol Strecker stent by Pocek, M, Maspes, F, Masala, S, Squillaci, E, Assegnati, G, Moraldi, A, Simonetti, G

    Published in European radiology
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  3. 3
    X‐ray mammography with synchrotron radiation

    X‐ray mammography with synchrotron radiation by Burattini, E., Gambaccini, M., Marziani, M., Rimondi, O., Indovina, P. L., Pocek, M., Simonetti, G., Benassi, M., Tirelli, C., Passariello, R.

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  4. 4
    Four Years' Follow-up Results of Three Different Percutaneous Treatments for Male Varicocele

    Four Years' Follow-up Results of Three Different Percutaneous Treatments for Male Varicocele by Pocek, M., Guazzaroni, M. R., Sodani, G., Guazzaroni, M. N., Cancellieri, R., Sakr, A. M. A., Simonetti, G.

    Published in Phlebology
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  5. 5
    Aktivnost radnih ljudi u samoupravljanju radnom organizacijom (Participation of Working People in the Self-Government of Work Organizations)

    Aktivnost radnih ljudi u samoupravljanju radnom organizacijom (Participation of Working People in the Self-Government of Work Organizations) by Kolaja, Jiri

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  6. 6
    Polymeric Formulas In Behavioral Pediatric Feeding Disorders

    Polymeric Formulas In Behavioral Pediatric Feeding Disorders by Novosel, D., Djurisic, V., Pocek, L., Adzic, M., Pekovic, D.

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  7. 7
    A Hardware Efficient Support Vector Machine Architecture for FPGA

    A Hardware Efficient Support Vector Machine Architecture for FPGA by Irick, K., DeBole, M., Narayanan, V., Gayasen, A.

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  8. 8
    A Structural Object Programming Model, Architecture, Chip and Tools for Reconfigurable Computing

    A Structural Object Programming Model, Architecture, Chip and Tools for Reconfigurable Computing by Butts, M., Jones, A.M., Wasson, P.

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  9. 9
    Generating FPGA-Accelerated DFT Libraries

    Generating FPGA-Accelerated DFT Libraries by D'Alberto, P., Milder, P.A., Sandryhaila, A., Franchetti, F., Hoe, J.C., Moura, J.M.F., Puschel, M., Johnson, J.R.

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  10. 10
    K-means Clustering for Multispectral Images Using Floating-Point Divide

    K-means Clustering for Multispectral Images Using Floating-Point Divide by Xiaojun Wang, Leeser, M.

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  11. 11
    Scaling Soft Processor Systems

    Scaling Soft Processor Systems by Labrecque, M., Yiannacouras, P., Steffan, J.G.

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  12. 12
    Autonomous System on a Chip Adaptation through Partial Runtime Reconfiguration

    Autonomous System on a Chip Adaptation through Partial Runtime Reconfiguration by French, M., Anderson, E., Dong-In Kang

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  13. 13
    A Data-Driven Approach for Pipelining Sequences of Data-Dependent Loops

    A Data-Driven Approach for Pipelining Sequences of Data-Dependent Loops by Rodrigues, R., Cardoso, J.M.P., Diniz, P.C.

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  14. 14
    An FPGA implementation of pipelined multiplicative division with IEEE Rounding

    An FPGA implementation of pipelined multiplicative division with IEEE Rounding by Goldberg, R., Even, G., Seidel, P.M.

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  15. 15
    An FPGA Implementation of Explicit-State Model Checking

    An FPGA Implementation of Explicit-State Model Checking by Fuess, M.E., Leeser, M., Leonard, T.

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  16. 16
    NAPA C: compiling for a hybrid RISC/FPGA architecture

    NAPA C: compiling for a hybrid RISC/FPGA architecture by Gokhale, M.B., Stone, J.M.

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  17. 17
    On the Acceleration of Shortest Path Calculations in Transportation Networks

    On the Acceleration of Shortest Path Calculations in Transportation Networks by Baker, Z.K., Gokhale, M.

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  18. 18
    The design and implementation of a context switching FPGA

    The design and implementation of a context switching FPGA by Scalera, S.M., Vazquez, J.R.

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  19. 19
    Writing Portable Applications that Dynamically Bind at Run Time to Reconfigurable Hardware

    Writing Portable Applications that Dynamically Bind at Run Time to Reconfigurable Hardware by Moore, N., Conti, A., Leeser, M., King, L.S.

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  20. 20
    Reconfigurable Work Farms on a Massively Parallel Processor Array

    Reconfigurable Work Farms on a Massively Parallel Processor Array by Butts, M., Budlong, B., Wasson, P., White, E.

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