Search Results - Pullakandam, Muralidhar

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  1. 1
    Empowering edge devices: FPGA‐based 16‐bit fixed‐point accelerator with SVD for CNN on 32‐bit memory‐limited systems

    Empowering edge devices: FPGA‐based 16‐bit fixed‐point accelerator with SVD for CNN on 32‐bit memory‐limited systems by Yanamala, Rama Muni Reddy, Pullakandam, Muralidhar

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  2. 2
    A high-speed reusable quantized hardware accelerator design for CNN on constrained edge device

    A high-speed reusable quantized hardware accelerator design for CNN on constrained edge device by Yanamala, Rama Muni Reddy, Pullakandam, Muralidhar

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  3. 3
    A Deep Learning Approach in Scalable High Efficiency Video Coding for Fast Coding Unit Size Decision

    A Deep Learning Approach in Scalable High Efficiency Video Coding for Fast Coding Unit Size Decision by Sairam, Sanagavarapu Karthik, Muralidhar, Pullakandam

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  4. 4
    Recursive Challenge Feed Arbiter Physical Unclonable Function (RC-FAPUF) In 180nm Process For Reliable Key Generation In IOT Security

    Recursive Challenge Feed Arbiter Physical Unclonable Function (RC-FAPUF) In 180nm Process For Reliable Key Generation In IOT Security by Podeti, Raveendra, Patri, Sreehari Rao, Pullakandam, Muralidhar

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  5. 5
    SoC-based real-time SVM classification with integrated training using HLS and PYNQ

    SoC-based real-time SVM classification with integrated training using HLS and PYNQ by B B, Shabarinath, Pullakandam, Muralidhar

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  6. 6
    Pipelined CORDIC Architecture Based DDFS Design and Implementation

    Pipelined CORDIC Architecture Based DDFS Design and Implementation by Verma, Sandeep Kumar, Pullakandam, Muralidhar, Yanamala, Rama Muni Reddy

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