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Evaluating Celerity: A 16-nm 695 Giga-RISC-V Instructions/s Manycore Processor With Synthesizable PLL
by
Rovinski, Austin
,
Veluri, Bandhav
,
Rao, Anuj
,
Ajayi, Tutu
,
Puscar, Julian
,
Dai, Steve
,
Zhao, Ritchie
,
Richmond, Dustin
,
Zhang, Zhiru
,
Galton, Ian
,
Batten, Christopher
,
Zhao, Chun
,
Taylor, Michael B.
,
Dreslinski, Ronald G.
,
Al-Hawaj, Khalid
,
Gao, Paul
,
Xie, Shaolin
,
Torng, Christopher
,
Davidson, Scott
,
Amarnath, Aporva
,
Vega, Luis
Published in
IEEE solid-state circuits letters
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A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS
by
Rovinski, Austin
,
Zhao, Chun
,
Al-Hawaj, Khalid
,
Gao, Paul
,
Xie, Shaolin
,
Torng, Christopher
,
Davidson, Scott
,
Amarnath, Aporva
,
Vega, Luis
,
Veluri, Bandhav
,
Rao, Anuj
,
Ajayi, Tutu
,
Puscar, Julian
,
Dai, Steve
,
Zhao, Ritchie
,
Richmond, Dustin
,
Zhang, Zhiru
,
Galton, Ian
,
Batten, Christopher
,
Taylor, Michael B
,
Dreslinski, Ronald G
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Ieee Solid-State Circuits Letters
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Engineering
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Engineering, Electrical & Electronic
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Science & Technology
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Technology
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Bandwidth
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Benchmark Testing
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Benchmarks
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Celerity
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Computer Architecture
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Computer Science
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Computer Science, Hardware & Architecture
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Energy Efficiency
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Manycore
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Manycore Processors
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Microprocessors
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Network-On-Chip
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Networks
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Risc
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2025
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Ieee Electronic Library (Iel) Conference Proceedings
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