PICO: automatically designing custom computers by Kathail, V., Aditya, S., Schreiber, R., Ramakrishna Rau, B., Cronquist, D.C., Sivaraman, M.

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EPIC: Explicitly Parallel Instruction Computing by Schlansker, M.S., Rau, B.R.

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Iterative modulo scheduling by RAMAKRISHNA RAU, B

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Embedded computer architecture and automation by Ramakrishna Rau, B., Schlansker, M.S.

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Constructing and exploiting linear schedules with prescribed parallelism by Darte, Alain, Schreiber, Robert, Rau, B. Ramakrishna, Vivien, Frédéric

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Instruction-level parallel processing: History, overview, and perspective by Rau, B. Ramakrishna, Fisher, Joseph A.

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Iterative modulo scheduling: an algorithm for software pipelining loops by Rau, B. Ramakrishna

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Optimization of machine descriptions for efficient use by GYLLENHAAL, J. C, HWU, W.-M. W, RAMAKRISHNA RAU, B

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Region-based compilation : Introduction, motivation, and initial experience by HANK, R. E, HWU, W.-M. W, RAMAKRISHNA RAU, B

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Region-based compilation: an introduction and motivation by Hank, R.E., Hwu, W.W., Rau, B.R.

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Code size minimization and retargetable assembly for custom EPIC and VLIW instruction formats by Aditya, Shail, Mahlke, Scott A., Rau, B. Ramakrishna

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Constructive solution to the juggling problem in processor array synthesis by Darte, Alain, Schreiber, Robert, Rau, B Ramakrishna, Vivien, Frederic

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Optimization of machine descriptions for efficient use by Gyllenhaal, John C, Hwu, Wen-mei W, Rau, B Ramakrishna

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Pseudo-randomly interleaved memory by Rau, B. Ramakrishna

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Compiling for EPIC architectures: Special Issue on Microprocessor Architecture and Compiler Technology by KATHAIL, Vinod, SCHLANSKER, Michael S, RAMAKRISHNA RAU, B

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Automatic Architectural Synthesis of VLIW and EPIC Processors by Aditya, Shail, Rau, B. Ramakrishna, Kathail, Vinod

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Code generation schema for modulo scheduled loops by Rau, B. Ramakrishna, Schlansker, Michael S., Tirumalai, P. P.

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The Cydra 5 departmental supercomputer: design philosophies, decisions, and trade-offs by Rau, B.R., Yen, D.W.L., Wei Yen, Towle, R.A.

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Iterative module scheduling: an algorithm for software pipelining loops by Ramakrishna Rau, B.

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Sentinel scheduling: a model for compiler-controlled speculative execution by Mahlke, Scott A., Chen, William Y., Bringmann, Roger A., Hank, Richard E., Hwu, Wen-Mei W., Rau, B. Ramakrishna, Schlansker, Michael S.

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