Search Results - Ramin Farjad-Rad

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  1. 1
    A 0.5-μm CMOS 4.0-Gbit/s serial link transceiver with data recovery using oversampling

    A 0.5-μm CMOS 4.0-Gbit/s serial link transceiver with data recovery using oversampling by Chih-Kong Ken Yang, Ramin Farjad-Rad, Horowitz, M.A.

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  2. 2
    A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips

    A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips by Farjad-Rad, R., Dally, W., Hiok-Tiaq Ng, Senthinathan, R., Lee, M.-J.E., Rathi, R., Poulton, J.

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  3. 3
    Jitter transfer characteristics of delay-locked loops - theories and design techniques

    Jitter transfer characteristics of delay-locked loops - theories and design techniques by Lee, M.-J.E., Dally, W.J., Greer, T., Hiok-Tiaq Ng, Farjad-Rad, R., Poulton, J., Senthinathan, R.

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  4. 4
    0.3- mu m CMOS 8-Gb/s 4-PAM serial link transceiver

    0.3- mu m CMOS 8-Gb/s 4-PAM serial link transceiver by Farjad-Rad, Ramin, Yang, Chih-Kong Ken, Horowitz, Mark A, Lee, Thomas H

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  5. 5
    A 0.4-μm CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter

    A 0.4-μm CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter by Farjad-Rad, R, Yang, C-K K, Horowitz, M A, Lee, T H

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  6. 6
    A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os

    A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os by Farjad-Rad, R., Nguyen, A., Tran, J.M., Greer, T., Poulton, J., Dally, W.J., Edmondson, J.H., Senthinathan, R., Rathi, R., Lee, M.-J.E., Hiok-Tiaq Ng

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  7. 7
    A second-order semidigital clock recovery circuit based on injection locking

    A second-order semidigital clock recovery circuit based on injection locking by Hiok-Tiaq Ng, Farjad-Rad, R., Lee, M.-J.E., Dally, W.J., Greer, T., Poulton, J., Edmondson, J.H., Rathi, R., Senthinathan, R.

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  8. 8
    A 0.2-2 GHz 12 mW multiplying DLL for low-jitter clock synthesis in highly-integrated data communication chips

    A 0.2-2 GHz 12 mW multiplying DLL for low-jitter clock synthesis in highly-integrated data communication chips by Farjad-Rad, R., Dally, W., Hoik-Tiaq Ng, Poulton, J., Stone, T., Rathi, R., Lee, E., Huang, D., Nathan, R.

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  9. 9
    A 0.5-/spl mu/m CMOS 4.0-Gbit/s serial link transceiver with data recovery using oversampling

    A 0.5-/spl mu/m CMOS 4.0-Gbit/s serial link transceiver with data recovery using oversampling by Chih-Kong Ken Yang, Ramin Farjad-Rad, Horowitz, M.A.

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  10. 10
    A 0.5-mu m CMOS 4.0-Gbit/s serial link transceiver with datarecovery using oversampling

    A 0.5-mu m CMOS 4.0-Gbit/s serial link transceiver with datarecovery using oversampling by Yang, Chih-Kong Ken, Farjad-Rad, Ramin, Horowitz, M A

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  11. 11
    A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR

    A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR by Leibowitz, Brian S., Kizer, Jade, Lee, Haechang, Chen, Fred, Ho, Andrew, Jeeradit, Metha, Bansal, Akash, Greer, Trey, Li, Simon, Farjad-Rad, Ramin, Stonecypher, William, Frans, Yohan, Daly, Barry, Heaton, Fred, Garlepp, Bruno W., Werner, Carl W., Nguyen, Nhat, Stojanovic, Vladimir, Zerbe, Jared L.

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