Search Results - Rangel-Patino, Francisco

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  1. 1
    System Margining Surrogate-Based Optimization in Post-Silicon Validation

    System Margining Surrogate-Based Optimization in Post-Silicon Validation by Rangel-Patino, Francisco Elias, Chavez-Hurtado, Jose Luis, Viveros-Wacher, Andres, Rayas-Sanchez, Jose Ernesto, Hakim, Nagib

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  2. 2
    Post-Silicon Receiver Equalization Metamodeling by Artificial Neural Networks

    Post-Silicon Receiver Equalization Metamodeling by Artificial Neural Networks by Rangel-Patino, Francisco Elias, Rayas-Sanchez, Jose Ernesto, Viveros-Wacher, Andres, Chavez-Hurtado, Jose Luis, Vega-Ochoa, Edgar Andrei, Hakim, Nagib

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  3. 3
    A Holistic Formulation for System Margining and Jitter Tolerance Optimization in Industrial Post-Silicon Validation

    A Holistic Formulation for System Margining and Jitter Tolerance Optimization in Industrial Post-Silicon Validation by Rangel-Patino, Francisco Elias, Viveros-Wacher, Andres, Rayas-Sanchez, Jose Ernesto, Duron-Rosales, Ismael, Vega-Ochoa, Edgar Andrei, Hakim, Nagib, Lopez-Miralrio, Enrique

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  4. 4
    Fast Jitter Tolerance Testing for High-Speed Serial Links in Post-Silicon Validation

    Fast Jitter Tolerance Testing for High-Speed Serial Links in Post-Silicon Validation by Viveros-Wacher, Andres, Baca-Baylon, Ricardo, Rangel-Patino, Francisco E., Silva-Cortes, Johana L., Vega-Ochoa, Edgar A., Rayas-Sanchez, Jose E.

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  5. 5
    Transmitter and Receiver Equalizers Optimization Methodologies for High-Speed Links in Industrial Computer Platforms Post-Silicon Validation

    Transmitter and Receiver Equalizers Optimization Methodologies for High-Speed Links in Industrial Computer Platforms Post-Silicon Validation by Rangel-Patino, Francisco E., Rayas-Sanchez, Jose E., Hakim, Nagib

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  6. 6
    Machine Learning Techniques and Space Mapping Approaches to Enhance Signal and Power Integrity in High-Speed Links and Power Delivery Networks

    Machine Learning Techniques and Space Mapping Approaches to Enhance Signal and Power Integrity in High-Speed Links and Power Delivery Networks by Rayas-Sanchez, Jose E., Rangel-Patino, Francisco E., Mercado-Casillas, Benjamin, Leal-Romo, Felipe, Chavez-Hurtado, Jose L.

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  7. 7
    Full RF characterization for extracting the small-signal equivalent circuit in microwave FETs

    Full RF characterization for extracting the small-signal equivalent circuit in microwave FETs by Reynoso-Hernandez, J.A., Rangel-Patino, F.E., Perdomo, J.

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  8. 8
    Reconfigurable FIR filter coefficient optimization in post-silicon validation to improve eye diagram for optical interconnects

    Reconfigurable FIR filter coefficient optimization in post-silicon validation to improve eye diagram for optical interconnects by Duron-Rosales, Ismael, Rangel-Patino, Francisco E., Rayas-Sanchez, Jose E., Chavez-Hurtado, Jose L., Hakim, Nagib

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  9. 9
    Jitter tolerance acceleration using the golden section optimization technique

    Jitter tolerance acceleration using the golden section optimization technique by Viveros-Wacher, Andres, Baca-Baylon, Ricardo, Rangel-Patino, Francisco E., Davalos-Santana, Miguel A., Vega-Ochoa, Edgar A., Rayas-Sanchez, Jose E.

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  10. 10
    Backplane/FDA correlation-FDA replacing commercial backplanes for SoC ethernet electrical validation

    Backplane/FDA correlation-FDA replacing commercial backplanes for SoC ethernet electrical validation by Mendoza-Bonilla, Jesus-Andres, Cortez-Ibarra, Alejandro, Vega-Ochoa, Edgar-Andrei, Rangel-Patino, Francisco, Gore, Brandon

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