Search Results - Reinman, G.

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  1. 1
    Fetch directed instruction prefetching

    Fetch directed instruction prefetching by Reinman, G., Calder, B., Austin, T.

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  2. 2
    Optimizations enabled by a decoupled front-end architecture

    Optimizations enabled by a decoupled front-end architecture by Reinman, G., Calder, B., Austin, T.

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  3. 3
    Predictive techniques for aggressive load speculation

    Predictive techniques for aggressive load speculation by Reinman, G., Calder, B.

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  4. 4
    CMP network-on-chip overlaid with multi-band RF-interconnect

    CMP network-on-chip overlaid with multi-band RF-interconnect by Chang, M.F., Cong, J., Kaplan, A., Naik, M., Reinman, G., Socher, E., Tam, S.-W.

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  5. 5
    Architecture support for accelerator-rich CMPs

    Architecture support for accelerator-rich CMPs by Cong, Jason, Ghodrat, Mohammad Ali, Gill, Michael, Grigorian, Beayna, Reinman, Glenn

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  6. 6
    Just say no: benefits of early cache miss determination

    Just say no: benefits of early cache miss determination by Memik, G., Reinman, G., Mangione-Smith, W.H.

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  7. 7
    Selective value prediction

    Selective value prediction by Calder, B., Reinman, G., Tullsen, D.M.

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  8. 8
    An energy-efficient adaptive hybrid cache

    An energy-efficient adaptive hybrid cache by Cong, J., Gururaj, K., Hui Huang, Chunyue Liu, Reinman, G., Yi Zou

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  9. 9
    A scalable front-end architecture for fast instruction delivery

    A scalable front-end architecture for fast instruction delivery by Reinman, G., Anstin, T., Calder, B.

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  10. 10
    Reducing the energy of speculative instruction schedulers

    Reducing the energy of speculative instruction schedulers by Yongxiang Liu, Memik, G., Reinman, G.

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  11. 11
    Accelerating Sequential Applications on CMPs Using Core Spilling

    Accelerating Sequential Applications on CMPs Using Core Spilling by Cong, Jason, Han, Guoling, Jagannathan, Ashok, Reinmany, Glenn, Rutkowski, Krzysztof

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  12. 12
    Reducing the latency and area cost of core swapping through shared helper engines

    Reducing the latency and area cost of core swapping through shared helper engines by Shayesteh, A., Kursun, E., Sherwood, T., Sair, S., Reinman, G.

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  13. 13
    Analysis of Noncoherent ASK Modulation-Based RF-Interconnect for Memory Interface

    Analysis of Noncoherent ASK Modulation-Based RF-Interconnect for Memory Interface by Yanghyo Kim, Sai-Wang Tam, Gyung-Su Byun, Hao Wu, Lan Nan, Reinman, G., Cong, J., Chang, M. F.

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  14. 14
    Power reduction of CMP communication networks via RF-interconnects

    Power reduction of CMP communication networks via RF-interconnects by Chang, M.-C.F., Cong, J., Kaplan, A., Chunyue Liu, Naik, M., Premkumar, J., Reinman, G., Socher, E., Sai-Wang Tam

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  15. 15
    The DIMM tree architecture: A high bandwidth and scalable memory system

    The DIMM tree architecture: A high bandwidth and scalable memory system by Therdsteerasukdi, K., Gyung-Su Byun, Ir, J., Reinman, G., Cong, J., Chang, M. F.

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  16. 16
    A 60GHz on-chip RF-Interconnect with λ/4 coupler for 5Gbps bi-directional communication and multi-drop arbitration

    A 60GHz on-chip RF-Interconnect with λ/4 coupler for 5Gbps bi-directional communication and multi-drop arbitration by Hao Wu, Lan Nan, Sai-Wang Tam, Hsieh-Hung Hsieh, Chewpu Jou, Reinman, G., Cong, J., Chang, M.-C F.

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  17. 17
    Utilizing Radio-Frequency Interconnect for a Many-DIMM DRAM System

    Utilizing Radio-Frequency Interconnect for a Many-DIMM DRAM System by Therdsteerasukdi, K., Gyung-Su Byun, Ir, J., Reinman, G., Cong, J., Chang, M. F.

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  18. 18
    An 8Gb/s/pin 4pJ/b/pin Single-T-Line dual (base+RF) band simultaneous bidirectional mobile memory I/O interface with inter-channel interference suppression

    An 8Gb/s/pin 4pJ/b/pin Single-T-Line dual (base+RF) band simultaneous bidirectional mobile memory I/O interface with inter-channel interference suppression by Yanghyo Kim, Gyung-Su Byun, Tang, A., Chewn-Pu Jou, Hsieh-Hung Hsieh, Reinman, G., Cong, J., Chang, M. F.

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  19. 19
    The Art of Deception: Adaptive Precision Reduction for Area Efficient Physics Acceleration

    The Art of Deception: Adaptive Precision Reduction for Area Efficient Physics Acceleration by Yeh, T.Y., Faloutsos, P., Ercegovac, M., Patel, S.J., Reinman, G.

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  20. 20
    Fine grain 3D integration for microarchitecture design through cube packing exploration

    Fine grain 3D integration for microarchitecture design through cube packing exploration by Yongxiang Liu, Yuchun Ma, Kursun, E., Reinman, G., Cong, J.

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