Search Results - Rixner, Scott

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  1. 1
    An FPGA Accelerator for Genome Variant Calling

    An FPGA Accelerator for Genome Variant Calling by Xu, Tiancheng, Rixner, Scott, Cox, Alan L.

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  2. 2
    Concurrent Direct Network Access for Virtual Machine Monitors

    Concurrent Direct Network Access for Virtual Machine Monitors by Willmann, P., Shafer, J., Carr, D., Menon, A., Rixner, S., Cox, A.L., Zwaenepoel, W.

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  3. 3
    Programmable stream processors

    Programmable stream processors by Kapasi, U.J., Rixner, S., Dally, W.J., Khailany, B., Jung Ho Ahn, Mattson, P., Owens, J.D.

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  4. 4
    Memory Controller Optimizations for Web Servers

    Memory Controller Optimizations for Web Servers by Rixner, Scott

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  5. 5
    SpecTLB: a mechanism for speculative address translation

    SpecTLB: a mechanism for speculative address translation by Barr, Thomas W., Cox, Alan L., Rixner, Scott

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  6. 6
    TPC: Target-Driven Parallelism Combining Prediction and Correction to Reduce Tail Latency in Interactive Services

    TPC: Target-Driven Parallelism Combining Prediction and Correction to Reduce Tail Latency in Interactive Services by Jeon, Myeongjae, He, Yuxiong, Kim, Hwanju, Elnikety, Sameh, Rixner, Scott, Cox, Alan L.

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  7. 7
    Imagine: media processing with streams

    Imagine: media processing with streams by Khailany, B., Dally, W.J., Kapasi, U.J., Mattson, P., Namkoong, J., Owens, J.D., Towles, B., Chang, A., Rixner, S.

    Published in IEEE MICRO
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  8. 8
    Reducing DRAM row activations with eager read/write clustering

    Reducing DRAM row activations with eager read/write clustering by Jeon, Myeongjae, Li, Conglong, Cox, Alan L., Rixner, Scott

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  9. 9
    Memory access scheduling

    Memory access scheduling by Rixner, Scott, Dally, William J., Kapasi, Ujval J., Mattson, Peter, Owens, John D.

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  10. 10
    Register organization for media processing

    Register organization for media processing by Rixner, S., Dally, W.J., Khailany, B., Mattson, P., Kapasi, U.J., Owens, J.D.

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  11. 11
    Reducing DRAM row activations with eager read/write clustering

    Reducing DRAM row activations with eager read/write clustering by Jeon, Myeongjae, Li, Conglong, Cox, Alan, Rixner, Scott

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  12. 12
    The Hadoop distributed filesystem: Balancing portability and performance

    The Hadoop distributed filesystem: Balancing portability and performance by Shafer, Jeffrey, Rixner, Scott, Cox, Alan L

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  13. 13
    Parallel Programmable Ethernet Controllers: Performance and Security

    Parallel Programmable Ethernet Controllers: Performance and Security by Schuff, Derek L, Pai, Vijay S, Willmann, Paul, Rixner, Scott

    Published in IEEE network
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  14. 14
    An FPGA Accelerator for Genome Variant Calling

    An FPGA Accelerator for Genome Variant Calling by Xu, Tiancheng, Rixner, Scott, Cox, Alan L.

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  15. 15
    A bandwidth-efficient architecture for media processing

    A bandwidth-efficient architecture for media processing by Rixner, S., Dally, W.J., Kapasi, U.J., Khailany, B., Lopez-Lagunas, A., Mattson, P.R., Owens, J.D.

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  16. 16
    Session details: Papers from WIOV

    Session details: Papers from WIOV

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  17. 17
    GMEM: Generalized Memory Management for Peripheral Devices

    GMEM: Generalized Memory Management for Peripheral Devices by Zhu, Weixi, Cox, Alan L, Rixner, Scott

    Published in arXiv.org
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  18. 18
    Parallel Programmable Ethernet Controllers: Performance and Security

    Parallel Programmable Ethernet Controllers: Performance and Security by Schuff, D.L., Pai, V.S., Willmann, P., Rixner, S.

    Published in IEEE network
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  19. 19
    Network interface data caching

    Network interface data caching by Kim, H., Rixner, S., Pai, V.S.

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  20. 20
    TCP offload through connection handoff

    TCP offload through connection handoff by KIM, Hyong-Youb, RIXNER, Scott

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