Search Results - Rogawski, Marcin

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  1. 1
    A high-speed unified hardware architecture for 128 and 256-bit security levels of AES and the SHA-3 candidate Grøstl

    A high-speed unified hardware architecture for 128 and 256-bit security levels of AES and the SHA-3 candidate Grøstl by Rogawski, Marcin, Gaj, Kris, Homsirikamol, Ekawat

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  2. 2
    Area-Time Efficient Implementation of the Elliptic Curve Method of Factoring in Reconfigurable Hardware for Application in the Number Field Sieve

    Area-Time Efficient Implementation of the Elliptic Curve Method of Factoring in Reconfigurable Hardware for Application in the Number Field Sieve by Gaj, Kris, Soonhak Kwon, Baier, Patrick, Kohlbrenner, Paul, Hoang Le, Khaleeluddin, Mohammed, Bachimanchi, Ramakrishna, Rogawski, Marcin

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  3. 3
    Hardware-software codesign of RSA for optimal performance vs. flexibility trade-off

    Hardware-software codesign of RSA for optimal performance vs. flexibility trade-off by Sharif, Malik Umar, Shahid, Rabia, Gaj, Kris, Rogawski, Marcin

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  4. 4
    A novel modular adder for one thousand bits and more using fast carry chains of modern FPGAs

    A novel modular adder for one thousand bits and more using fast carry chains of modern FPGAs by Rogawski, Marcin, Homsirikamol, Ekawat, Gaj, Kris

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  5. 5
    A High-Speed Unified Hardware Architecture for AES and the SHA-3 Candidate Grøstl

    A High-Speed Unified Hardware Architecture for AES and the SHA-3 Candidate Grøstl by Rogawski, M., Gaj, K.

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  6. 6
    Efficient Hardware Accelerator for IPSec Based on Partial Reconfiguration on Xilinx FPGAs

    Efficient Hardware Accelerator for IPSec Based on Partial Reconfiguration on Xilinx FPGAs by Salman, A., Rogawski, M., Kaps, J.

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  7. 7
    ATHENa - Automated Tool for Hardware EvaluatioN: Toward Fair and Comprehensive Benchmarking of Cryptographic Hardware Using FPGAs

    ATHENa - Automated Tool for Hardware EvaluatioN: Toward Fair and Comprehensive Benchmarking of Cryptographic Hardware Using FPGAs by Gaj, K, Kaps, J, Amirineni, V, Rogawski, M, Homsirikamol, E, Brewster, B Y

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  8. 8
    Use of embedded FPGA resources in implementations of 14 round 2 SHA-3 candidates

    Use of embedded FPGA resources in implementations of 14 round 2 SHA-3 candidates by Shahid, R., Sharif, M. U., Rogawski, M., Gaj, K.

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  9. 9
    Analysis of Implementation Hierocrypt-3 algorithm (and its comparison to Camellia algorithm) using ALTERA devices

    Analysis of Implementation Hierocrypt-3 algorithm (and its comparison to Camellia algorithm) using ALTERA devices by Rogawski, Marcin

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