Fault Tolerance Evaluation of Different Majority Voter Designs by Oliveira, Ingrid F. V., Pontes, Matheus F., Schvittz, Rafael B., Rosa, Leomar S., Butzen, Paulo F., Soares, Rafael I.

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Evaluating the Reliability of Different Voting Schemes for Fault Tolerant Approximate Systems by Balen, Tiago R., González, Carlos J., Oliveira, Ingrid F. V., da Rosa Jr, Leomar S., Soares, Rafael I., Schvittz, Rafael B., Added, Nemitala, Macchione, Eduardo L. A., Aguiar, Vitor A. P., Guazzelli, Marcilei A., Medina, Nilberto H., Butzen, Paulo F.

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DRAPS: A Design Rule Aware Path Search Algorithm for Detailed Routing by Goncalves, Stephano M. M., Rosa, Leomar S., Marques, Felipe S.

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SmartDR: Algorithms and Techniques for Fast Detailed Routing with Good Design Rule Handling by Gonçalves, Stèphano M. M., Rosa Jr, Leomar S. da, Marques, Felipe S.

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The Impact of Logic Gates Susceptibility in Overall Circuit Reliability Analysis by Pontes, Matheus F., Oliveira, Ingrid F. V., Schvittz, Rafael B., Rosa, Leomar S., Butzen, Paulo F.

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Libra: An Automatic Design Methodology for CMOS Complex Gates by Cardoso, Maicon S., Smaniotto, Gustavo H., Bubolz, Andrei A. O., Moreira, Matheus T., da Rosa, Leomar S., Marques, Felipe de S.

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Methods for Susceptibility Analysis of Logic Gates in the Presence of Single Event Transients by Schvittz, Rafael B., Butzen, Paulo F., Rosa, Leomar S. da

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Calibration of Logical Effort Transistor Sizing for On-the-Fly Low-Power Supergate Design by Kessler, Henrique, Bohlke, Murilo, da Rosa, Leomar S., Porto, Marcelo, Camargo, Vinicius V.

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A Fast Approximate Function Generation Method to ATMR Architecture by Manske, Guilherme B., Farias, Clayton R., Butzen, Paulo F., da Rosa, Leomar S.

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Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization by Rai, Shubham, Neto, Walter Lau, Miyasaka, Yukio, Zhang, Xinpei, Yu, Mingfei, Yi, Qingyang, Fujita, Masahiro, Manske, Guilherme B., Pontes, Matheus F., da Rosa, Leomar S., de Aguiar, Marilton S., Butzen, Paulo F., Chien, Po-Chun, Huang, Yu-Shan, Wang, Hoa-Ren, Jiang, Jie-Hong R., Gu, Jiaqi, Zhao, Zheng, Jiang, Zixuan, Pan, David Z., de Abreu, Brunno A., de Souza Campos, Isac, Berndt, Augusto, Meinhardt, Cristina, Carvalho, Jonata T., Grellert, Mateus, Bampi, Sergio, Lohana, Aditya, Kumar, Akash, Zeng, Wei, Davoodi, Azadeh, Topaloglu, Rasit O., Zhou, Yuan, Dotzel, Jordan, Zhang, Yichi, Wang, Hanyu, Zhang, Zhiru, Tenace, Valerio, Gaillardon, Pierre-Emmanuel, Mishchenko, Alan, Chatterjee, Satrajit

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Transistor placement strategies for non-series-parallel cells by Cardoso, Maicon S., Smaniotto, Gustavo H., Machado, Joao J. da S., Moreira, Matheus T., da Rosa, Leomar S., Marques, Felipe de S.

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Transistor Count Optimization in IG FinFET Network Design by Possani, Vinicius N., Reis, Andre I., Ribas, Renato P., Marques, Felipe S., da Rosa, Leomar S.

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An Improved Heuristic Function for A∗-Based Path Search in Detailed Routing by Goncalves, Stephano M. M., da Rosa, Leomar S., de S. Marques, Felipe

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Standby power consumption estimation by interacting leakage current mechanisms in nanoscaled CMOS digital circuits by Butzen, Paulo F., da Rosa, Leomar S., Chiappetta Filho, Erasmo J.D., Reis, André I., Ribas, Renato P.

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Toward better layout design in ASTRAN CAD tool by using an efficient transistor folding by Smaniotto, Gustavo H., Moreira, Matheus T., Ziesemer, Adriel M., Marques, Felipe S., da Rosa, Leomar S.

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Optimizing transistor networks using a graph-based technique by Possani, Vinicius N., de Souza, Renato S., Domingues, Julio S., Agostini, Luciano V., Marques, Felipe S., da Rosa, Leomar S.

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Physical design of supergate cells aiming geometrical optimizations by Cardoso, Maicon S., Smaniotto, Gustavo H., Zanandrea, Regis, de Souza, Renato S., da Rosa, Leomar S., Marques, Felipe de S.

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A Media Processing Implementation Using Libvlc for the Ginga Middleware by Trojahn, Tiago H., Goncalves, Juliano L., Mattos, Julio C. B., Da Rosa Junior, Leomar S., Agostini, Luciano V.

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Switch level optimization of digital CMOS gate networks by da Rosa, L.S., Schneider, F.R., Ribas, R.P., Reis, A.I.

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NSP kernel finder - A methodology to find and to build non-series-parallel transistor arrangements by Possani, V. N., Marques, F. S., da Rosa, L. S., Callegaro, V., Reis, A. I., Ribas, R. P.

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