Search Results - Runde, Zhou

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  1. 1
    A High-Speed Two-Cell BCH Decoder for Error Correcting in MLC nor Flash Memories

    A High-Speed Two-Cell BCH Decoder for Error Correcting in MLC nor Flash Memories by Xueqiang, Wang, Liyang, Pan, Dong, Wu, Chaohong, Hu, Runde, Zhou

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  2. 2
    Low Latency High Throughout Circular Asynchronous FIFO

    Low Latency High Throughout Circular Asynchronous FIFO by Xiao, Yong, Zhou, Runde

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  3. 3
    a new type of high-performance low-power low clock-swing TSPC flip-flop

    a new type of high-performance low-power low clock-swing TSPC flip-flop by Yingbo Hu, Zhaolin Li, Runde Zhou

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  4. 4
    A high efficiency CMOS charge pump for low voltage operation

    A high efficiency CMOS charge pump for low voltage operation by Xueqiang Wang, Dong Wu, Fengying Qiao, Peng Zhu, Kan Li, Liyang Pan, Runde Zhou

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  5. 5
    Embedded high-speed BCH decoder for new-generation NOR flash memories

    Embedded high-speed BCH decoder for new-generation NOR flash memories by Xueqiang Wang, Dong Wu, Chaohong Hu, Liyang Pan, Runde Zhou

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  6. 6
    Low power inductor-less pulse UWB transceiver

    Low power inductor-less pulse UWB transceiver by Mengmeng Liu, Sheng Zhang, Shuo Wang, Jianliang Zhang, Runde Zhou

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  7. 7
    Design of a fully pipelined single-precision floating-point unit

    Design of a fully pipelined single-precision floating-point unit by Zhaolin Li, Xinyue Zhang, Gongqiong Li, Runde Zhou

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  8. 8
    A fully integrated CMOS UWB transmitter

    A fully integrated CMOS UWB transmitter by Jianliang Zhang, Sheng Zhang, Shuo Wang, Jianming qiu, Runde Zhou

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  9. 9
    A fully-integrated CMOS UWB transceiver for ultra-low-power short-range application

    A fully-integrated CMOS UWB transceiver for ultra-low-power short-range application by Liu, Mengmeng, Zhang, Sheng, Wang, Shuo, Zhou, Runde

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  10. 10
    A transition entropy area estimation method for combinational circuits

    A transition entropy area estimation method for combinational circuits by Zhang Sheng, Wang Nailong, Zhou Runde

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  11. 11
    Power analysis and optimization methods of the pipelined array multiplier

    Power analysis and optimization methods of the pipelined array multiplier by Zhang Sheng, Wang Nailong, Zhou Runde

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  12. 12
    A novel built-in CMOS sensor for on-line thermal monitoring of VLSI circuits

    A novel built-in CMOS sensor for on-line thermal monitoring of VLSI circuits by Wang Nailong, Zhang Sheng, Zhou Runde

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  13. 13
    Physical implementation and test of energy recovery circuit

    Physical implementation and test of energy recovery circuit by Dai Hongyu, Zhang Sheng, Zhou Runde

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  14. 14
    The design of an improved low-power voltage testing and protection circuit

    The design of an improved low-power voltage testing and protection circuit by Wang Nailong, Zhang Sheng, Zhou Runde

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  15. 15
    Asynchronous trigger reception algorithm for low-power UWB system

    Asynchronous trigger reception algorithm for low-power UWB system by Liu Mengmeng, Wang Shuo, Zhou Runde

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  16. 16
    An on-chip high-speed 4-bit BCH decoder in MLC NOR flash memories

    An on-chip high-speed 4-bit BCH decoder in MLC NOR flash memories by Xueqiang Wang, Dong Wu, Liyang Pan, Runde Zhou, Chaohong Hu

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  17. 17
    Improved energy recovery logic for low power computation

    Improved energy recovery logic for low power computation by Dai Hongyu, Zhou Runde

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  18. 18
    An MBOK-UWB SoC transceiver in 0.181μm CMOS technology

    An MBOK-UWB SoC transceiver in 0.181μm CMOS technology by Sheng Zhang, Jianliang Zhang, Mengmeng Liu, Shuo Wang, Liang Heng, Runde Zhou

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  19. 19
    Low-power motion-estimation architecture based on a novel early-jump-out technique

    Low-power motion-estimation architecture based on a novel early-jump-out technique by Wujian Zhang, Runde Zhou, Kondo, T.

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  20. 20
    Single-track asynchronous pipeline controller design

    Single-track asynchronous pipeline controller design by Xiao Yong, Zhou Runde

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