Search Results - SOMAYAJI, Ananth

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  1. 1
    Role of intramuscular injections of vasopressors in combating spinal hypotension during caesarean sections: A prospective, randomized, double-blinded controlled clinical trial

    Role of intramuscular injections of vasopressors in combating spinal hypotension during caesarean sections: A prospective, randomized, double-blinded controlled clinical trial by Ananth Srikrishna Somayaji, Gayathri Bhat

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  2. 2
    Intraperitoneal instillation versus port-site infiltration or subcostal transversus abdominis plane block for post-operative analgesia following laparoscopic cholecystectomy

    Intraperitoneal instillation versus port-site infiltration or subcostal transversus abdominis plane block for post-operative analgesia following laparoscopic cholecystectomy by D’Cunha, Delma, Somayaji, Ananth S.

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  3. 3
    Survey of practice patterns of airway management: A comparison between academic and nonacademic setups in Karnataka

    Survey of practice patterns of airway management: A comparison between academic and nonacademic setups in Karnataka by Somayaji, Ananth, Raveendra, U

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  4. 4
    Effect of dexmedetomidine on blood loss and quality of surgical field in functional endoscopic sinus surgery: A double blinded prospective controlled study

    Effect of dexmedetomidine on blood loss and quality of surgical field in functional endoscopic sinus surgery: A double blinded prospective controlled study by Somayaji, Ananth, Raveendra, U

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  5. 5
    Design for degradation: CAD tools for managing transistor degradation mechanisms

    Design for degradation: CAD tools for managing transistor degradation mechanisms by Goda, A.S., Kapila, G.

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  6. 6
    High voltage ESD protection strategies for USB and PCI applications for 180nm/130nm/90nm CMOS technologies

    High voltage ESD protection strategies for USB and PCI applications for 180nm/130nm/90nm CMOS technologies by Jahanzeb, A., Duvvury, C., Cline, R., Sterrantino, S., Kothamasu, S., Somayaji, A.

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  7. 7
    A Fail-Safe ESD protection circuit with 230 fF linear capacitance for high-speed/high-precision 0.18 μm CMOS I/O application

    A Fail-Safe ESD protection circuit with 230 fF linear capacitance for high-speed/high-precision 0.18 μm CMOS I/O application by LIN, Jerry Heng-Chih, DUVVURY, Charvaka, HAROUN, Baher, OGUZMAN, Ismail, SOMAYAJI, Ananth

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