Four‐Dimensional Design Space of High‐Q Second‐Order Distributed Feedback Perovskite Lasers by Annavarapu, Nirav, Goldberg, Iakov, Hamdad, Sarah, Elkhouly, Karim, Puybaret, Renaud, Sabuncuoglu Tezcan, Deniz, Genoe, Jan, Gehlhaar, Robert, Heremans, Paul

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Wafer reconstitution: embedded multi-die III-V and silicon co-integration platform by Karve, Gauri, Li, Yunlong, Motsnyi, Vasyl, Wei, Wei, Visker, Jakob, Chancerel, François, Ackaert, Jan, Puybaret, Renaud, Dutta, Barundeb, Sabuncuoglu Tezcan, Deniz, Peng, Lan, Soussan, Philippe, Severi, Simone, Osman, Haris

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Micro vapor bubble jet flow for safe and high-rate fluorescence-activated cell sorting by de Wijs, Koen, Liu, Chengxun, Dusa, Alexandra, Vercruysse, Dries, Majeed, Bivragh, Tezcan, Deniz Sabuncuoglu, Blaszkiewicz, Kamil, Loo, Josine, Lagae, Liesbet

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Low-cost uncooled infrared detectors in CMOS process by Eminoglu, Selim, Tezcan, Deniz Sabuncuoglu, Tanrikulu, M.Yusuf, Akin, Tayfun

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First Demonstration of Hybrid CMOS Imagers With Simultaneous Very Low Crosstalk and High-Broadband Quantum Efficiency by Minoglou, K., De Munck, K., De Vos, J., Tezcan, D. S., Van Hoof, C., De Moor, P.

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3-D Wafer-Level Packaging Die Stacking Using Spin-on-Dielectric Polymer Liner Through-Silicon Vias by Civale, Y, Tezcan, D S, Philipsen, H G G, Duval, F F C, Jaenen, P, Travaly, Y, Soussan, P, Swinnen, B, Beyne, E

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On the processing aspects of high performance hybrid backside illuminated CMOS imagers by De Vos, Joeri, De Munck, Koen, Minoglou, Kiki, Rao, Padmakumar Ramachandra, Erismis, Mehmet Akif, De Moor, Piet, Tezcan, Deniz Sabuncuoglu

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(Invited) Through-Silicon Via Technology for 3D Applications by Philipsen, Harold G., Lühn, Ole, Civale, Yann, Wang, Yu-Shuen, Sabuncuoglu Tezcan, Deniz, Ruythooren, Wouter

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Micro vapor bubble jet flow for safe and high-rate fluorescence-activated cell sortingElectronic supplementary information (ESI) available. See DOI: 10.1039/c6lc01560c by de Wijs, Koen, Liu, Chengxun, Dusa, Alexandra, Vercruysse, Dries, Majeed, Bivragh, Tezcan, Deniz Sabuncuoglu, Blaszkiewicz, Kamil, Loo, Josine, Lagae, Liesbet

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Highly Selective Color Filters Based on Hybrid Plasmonic–Dielectric Nanostructures by De Proft, Anabel, Lodewijks, Kristof, Figeys, Bruno, Kouznetsov, Dmitry, Verellen, Niels, Pham, Nga P, Vereecke, Bart, Sabuncuoglu Tezcan, Deniz, Jansen, Roelof, Van Dorpe, Pol, Rottenberg, Xavier

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Wafer Level Pixelation of Colloidal Quantum Dot Image Sensors by Li, Yunlong, Karve, Gauri, Malinowski, Pawel E., Kim, Joo Hyoung, Georgitzikis, Epimitheas, Pejovic, Vladimir, Lim, Myung-Jin, Hagelsieb, Luis Moreno, Puybaret, Renaud, Lieberman, Itai, Lee, Jiwon, Cheyns, David, Heremans, Paul, Osman, Haris, Tezcan, Deniz Sabuncuoglu

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Copper Oxide Direct Bonding of 200mm CMOS Wafers with Five Metal Levels and TSVs: Morphological and Electrical Characterization by Cavaco, Celso, Peng, Lan, Lavizzari, Simone, Claes, Jesse, Hoovels, Nele V., Guerrieri, Stefano, Tezcan, Deniz Sabuncuoglu, Osman, Haris

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The RELAXd project: Development of four-side tilable photon-counting imagers by Vykydal, Zdenek, Visschers, Jan, Tezcan, Deniz Sabuncuoglu, De Munck, Koen, Borgers, Tom, Ruythooren, Wouter, De Moor, Piet

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A low-cost uncooled infrared microbolometer detector in standard CMOS technology by Tezcan, D.S., Eminoglu, S., Akin, T.

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On the Fabrication of Backside Illuminated Image Sensors: Bonding Oxide, Edge Trimming and CMP Rework Routes by Cavaco, Celso, Peng, Lan, Sebaai, Farid, Verbinnen, Greet, Visker, Jakob, Olmen, Jan, Tezcan, Deniz Sabuncuoglu, Osman, Haris

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Through-silicon via and die stacking technologies for microsystems-integration by Beyne, E., De Moor, P., Ruythooren, W., Labie, R., Jourdain, A., Tilmans, H., Tezcan, D.S., Soussan, P., Swinnen, B., Cartuyvels, R.

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Wafer Scale Processing of Plasmonic Nanoslit Arrays in 200mm CMOS Fab Environment by Malachowski, Karl, Verbeeck, Rita, Dupont, Tania, Chen, Chang, Li, Yi, Musa, Silke, Stakenborg, Tim, Sabuncuoglu Tezcan, Deniz, Van Dorpe, Pol

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Electrical characterization, modeling and reliability analysis of a via last TSV by Majeed, B, Sabuncuoglu Tezcan, Deniz, Vandevelde, B, Duval, F, Soussan, P, Beyne, E

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Use of Polymer Liners for 3D-WLP TSVs: Process, Reliability and Cost by Sabuncuoglu Tezcan, Deniz, Pham, Nga P., Majeed, Bivragh, Civale, Yann, Beyne, Eric

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CMOS Compatible Anodization Process for Low Cost High Density Capacitors by Detalle, Mikael, Rakowski, Michal, Potoms, Goedele, Mercha, Abdelkarim, De Potter de ten Broeck, Muriel, Phommahaxay, Alain, Sabuncuoglu Tezcan, Deniz, Soussan, Philippe

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