Search Results - Sadeghi, Rezgar

  • Showing 1 - 8 results of 8
Refine Results
  1. 1
    LUT Input Reordering to Reduce Aging Impact on FPGA LUTs

    LUT Input Reordering to Reduce Aging Impact on FPGA LUTs by Ebrahimi, Mohammad, Sadeghi, Rezgar, Navabi, Zainalabedin

    Get full text
    Items that this one cites
    Items that cite this one
    Article
    Save to List
    Saved in:
  2. 2
    ESL, Back-annotating Crosstalk Fault Models into High-level Communication Links

    ESL, Back-annotating Crosstalk Fault Models into High-level Communication Links by Basharkhah, Katayoon, Sadeghi, Rezgar, Nosrati, Nooshin, Navabi, Zainalabedin

    Request full text
    Conference Proceeding
    Save to List
    Saved in:
  3. 3
    Built-In Predictors for Dynamic Crosstalk Avoidance

    Built-In Predictors for Dynamic Crosstalk Avoidance by Sadeghi, Rezgar, Navabi, Zainalabedin

    Request full text
    Conference Proceeding
    Save to List
    Saved in:
  4. 4
    On-Chip Training of Crosstalk Predictors to Fit Uncertainties

    On-Chip Training of Crosstalk Predictors to Fit Uncertainties by Sadeghi, Rezgar, Akbari, Ehsan, Ali Saber, Mohamad

    Request full text
    Conference Proceeding
    Save to List
    Saved in:
  5. 5
    Back-annotation of Interconnect Physical Properties for System-Level Crosstalk Modeling

    Back-annotation of Interconnect Physical Properties for System-Level Crosstalk Modeling by Sadeghi, Rezgar, Nosrati, Nooshin, Basharkhah, Katayoon, Navabi, Zainalabedin

    Request full text
    Conference Proceeding
    Save to List
    Saved in:
  6. 6
    An ESL Environment for Modeling Electrical Interconnect Faults

    An ESL Environment for Modeling Electrical Interconnect Faults by Nosrati, Nooshin, Basharkhah, Katayoon, Sadeghi, Rezgar, Navabi, Zainalabedin

    Request full text
    Conference Proceeding
    Save to List
    Saved in:
  7. 7
    An Accelerator-based Architecture Utilizing an Efficient Memory Link for Modern Computational Requirements

    An Accelerator-based Architecture Utilizing an Efficient Memory Link for Modern Computational Requirements by Yousefzadeh, Saba, Basharkhah, Katayoon, Nosrati, Nooshin, Sadeghi, Rezgar, Raik, Jaan, Jenihhin, Maksim, Navabi, Zainalabedin

    Request full text
    Conference Proceeding
    Save to List
    Saved in:
  8. 8
    Making System Level Test Possible by a Mixed-mode, Multi-level, Integrated Modeling Environment

    Making System Level Test Possible by a Mixed-mode, Multi-level, Integrated Modeling Environment by Nosrati, Nooshin, Basharkhah, Katayoon, Sadeghi, Rezgar, Zivkovic, Carna, Grimm, Christoph, Navabi, Zainalabedin

    Request full text
    Conference Proceeding
    Save to List
    Saved in:

Search Tools: