Search Results - Saggese, G.P.

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  1. 1
    An experimental study of soft errors in microprocessors

    An experimental study of soft errors in microprocessors by Saggese, G.P., Wang, N.J., Kalbarczyk, Z.T., Patel, S.J., Iyer, R.K.

    Published in IEEE MICRO
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  2. 2
    Exploring the design-space for FPGA-based implementation of RSA

    Exploring the design-space for FPGA-based implementation of RSA by Cilardo, A., Mazzeo, A., Romano, L., Saggese, G.P.

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  3. 3
    Microprocessor sensitivity to failures: control vs. execution and combinational vs. sequential logic

    Microprocessor sensitivity to failures: control vs. execution and combinational vs. sequential logic by Saggese, G.P., Vetteth, A., Kalbarczyk, Z., Ravishankar Iyer

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  4. 4
    FPGA-based implementation of a serial RSA processor

    FPGA-based implementation of a serial RSA processor by Mazzeo, A., Romano, L., Saggese, G.P., Mazzocca, N.

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  5. 5
    A tamper resistant hardware accelerator for RSA cryptographic applications

    A tamper resistant hardware accelerator for RSA cryptographic applications by Saggese, G.P., Romano, L., Mazzocca, N., Mazzeo, A.

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  6. 6
    Carry-save Montgomery modular exponentiation on reconfigurable hardware

    Carry-save Montgomery modular exponentiation on reconfigurable hardware by Cilardo, A., Mazzeo, A., Romano, L., Saggese, G.P.

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  7. 7
    An FPGA-based key-store for improving the dependability of security services

    An FPGA-based key-store for improving the dependability of security services by Cilardo, A., Mazzeo, A., Romano, L., Saggese, G.P.

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  8. 8
    Hardware support for high performance, intrusion- and fault-tolerant systems

    Hardware support for high performance, intrusion- and fault-tolerant systems by Saggese, G.P., Basile, C., Romano, L., Kalbarczyk, Z., Iyer, R.K.

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  9. 9
    Dynamic Derivation of Application-Specific Error Detectors and their Implementation in Hardware

    Dynamic Derivation of Application-Specific Error Detectors and their Implementation in Hardware by Pattabiraman, K., Saggese, G.P., Chen, D., Kalbarczyk, Z., Iyer, R.K.

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  10. 10
    Shuffled serial adder: an area-latency effective serial adder

    Shuffled serial adder: an area-latency effective serial adder by Saggese, G.P., Strollo, A.G.M., Mazzocca, N., De Caro, D.

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  11. 11
    A reconfigurable 2D convolver for real-time SAR imaging

    A reconfigurable 2D convolver for real-time SAR imaging by Strollo, A.G.M., Napoli, E., De Caro, D., Saggese, G.P.

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  12. 12
    Test pattern generator for hybrid testing of combinational circuits

    Test pattern generator for hybrid testing of combinational circuits by De Caro, D., Mazzocca, N., Napoli, E., Saggese, G.P., Strollo, A.G.M.

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