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Simplistic Simulation-Based Device-VT-Targeting Technique to Determine Technology High-Density LELE-Gate-Patterned FinFET SRAM in Sub-10 nm Era
by
Sakhare, Sushil Sudam
,
Miyaguchi, Kenichi
,
Raghavan, Praveen
,
Mercha, Abdelkarim
Published in
IEEE transactions on electron devices
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Ieee Transactions On Electron Devices
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10-Nm Technology
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Capacitance
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Computer Architecture
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Design Methodology
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Design Technology Co-Optimization
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Double Patterning Gate
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Engineering
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Engineering, Electrical & Electronic
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Finfet Sram Design
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Finfets
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High Density
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Logic Gates
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Metals
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Physical Sciences
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Physics
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Physics, Applied
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Science & Technology
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Self-Aligned Double Patterning
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Self-Aligned Quadruple Patterning
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Sram Cells
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Ieee Electronic Library (Iel) Journals
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