Extended Methodology to Determine SRAM Write Margin in Resistance-Dominated Technology Node by Liu, Hsiao-Hsuan, Salahuddin, Shairfe M., Abdi, Dawit, Chen, Rongmei, Weckx, Pieter, Matagne, Philippe, Catthoor, Francky

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3D SRAM Macro Design in 3D Nanofabric Process Technology by Abdi, Dawit Burusie, Salahuddin, Shairfe M., Boemmels, Juergen, Giacomin, Edouard, Weckx, Pieter, Ryckaert, Julien, Hellings, Geert, Catthoor, Francky

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SRAM With Buried Power Distribution to Improve Write Margin and Performance in Advanced Technology Nodes by Salahuddin, Shairfe M., Shaik, Khaja A., Gupta, Anshul, Chava, Bharani, Gupta, Mohit, Weckx, Pieter, Ryckaert, Julien, Spessot, Alessio

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CFET SRAM DTCO, Interconnect Guideline, and Benchmark for CMOS Scaling by Liu, Hsiao-Hsuan, Salahuddin, Shairfe M., Chan, Boon Teik, Schuddinck, Pieter, Xiang, Yang, Hellings, Geert, Weckx, Pieter, Ryckaert, Julien, Catthoor, Francky

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Future Design Direction for SRAM Data Array: Hierarchical Subarray With Active Interconnect by Liu, Hsiao-Hsuan, Gilardi, Carlo, Salahuddin, Shairfe M., Pei, Zhenlin, Schuddinck, Pieter, Xiang, Yang, Weckx, Pieter, Hellings, Geert, Bardon, Marie Garcia, Ryckaert, Julien, Pan, Chenyun, Mitra, Subhasish, Catthoor, Francky

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CFET SRAM With Double-Sided Interconnect Design and DTCO Benchmark by Liu, Hsiao-Hsuan, Schuddinck, Pieter, Pei, Zhenlin, Verschueren, Lynn, Mertens, Hans, Salahuddin, Shairfe M., Hiblot, Gaspard, Xiang, Yang, Chan, Boon Teik, Subramanian, Sujith, Weckx, Pieter, Hellings, Geert, Bardon, Marie Garcia, Ryckaert, Julien, Pan, Chenyun, Catthoor, Francky

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