Search Results - Saluja, K.K.

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  1. 1
    Fault tolerance in collaborative sensor networks for target detection

    Fault tolerance in collaborative sensor networks for target detection by Clouqueur, T., Saluja, K.K., Ramanathan, P.

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  2. 2
    On low-capture-power test generation for scan testing

    On low-capture-power test generation for scan testing by Xiaoqing Wen, Yamashita, Y., Kajihara, S., Laung-Terng Wang, Saluja, K.K., Kinoshita, K.

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  3. 3
    Modeling Detection Latency with Collaborative Mobile Sensing Architecture

    Modeling Detection Latency with Collaborative Mobile Sensing Architecture by Tai-Lin Chin, Ramanathan, P., Saluja, K.K.

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  4. 4
    Optimizing program disturb fault tests using defect-based testing

    Optimizing program disturb fault tests using defect-based testing by Mohammad, M.Gh, Saluja, K.K.

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  5. 5
    On diagnosing multiple stuck-at faults using multiple and single fault simulation in combinational circuits

    On diagnosing multiple stuck-at faults using multiple and single fault simulation in combinational circuits by Takahashi, H., Boateng, K.O., Saluja, K.K., Takamatsu, Y.

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  6. 6
    Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester

    Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester by Nakamura, Y., Clouqueur, T., Saluja, K.K., Fujiwara, H.

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  7. 7
    Simulating program disturb faults in flash memories using SPICE compatible electrical model

    Simulating program disturb faults in flash memories using SPICE compatible electrical model by Mohammad, M.G., Saluja, K.K.

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  8. 8
    A method for reducing the target fault list of crosstalk faults in synchronous sequential circuits

    A method for reducing the target fault list of crosstalk faults in synchronous sequential circuits by Takahashi, H., Keller, K.J., Le, K.T., Saluja, K.K., Takamatsu, Y.

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  9. 9
    Combinational automatic test pattern generation for acyclic sequential circuits

    Combinational automatic test pattern generation for acyclic sequential circuits by Yong Chang Kim, Agrawal, V.D., Saluja, K.K.

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  10. 10
    Instruction-Based Self-Testing of Delay Faults in Pipelined Processors

    Instruction-Based Self-Testing of Delay Faults in Pipelined Processors by Singh, V., Inoue, M., Saluja, K.K., Fujiwara, H.

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  11. 11
    Scheduling tests for VLSI systems under power constraints

    Scheduling tests for VLSI systems under power constraints by Chou, R.M., Saluja, K.K., Agrawal, V.D.

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  12. 12
    Simulation-based diagnosis for crosstalk faults in sequential circuits

    Simulation-based diagnosis for crosstalk faults in sequential circuits by Takahashi, H., Phadoongsidhi, M., Higami, Y., Saluja, K.K., Takamatsu, Y.

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  13. 13
    Low-capture-power test generation for scan-based at-speed testing

    Low-capture-power test generation for scan-based at-speed testing by Xiaoqing Wen, Yamashita, Y., Morishima, S., Kajihara, S., Laung-Terng Wang, Saluja, K.K., Kinoshita, K.

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  14. 14
    Partition Based SoC Test Scheduling with Thermal and Power Constraints under Deep Submicron Technologies

    Partition Based SoC Test Scheduling with Thermal and Power Constraints under Deep Submicron Technologies by Chunhua Yao, Saluja, K.K., Ramanathan, P.

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  15. 15
    A new ATPG method for efficient capture power reduction during scan testing

    A new ATPG method for efficient capture power reduction during scan testing by Xiaoqing Wen, Kajihara, S., Miyase, K., Suzuki, T., Saluja, K.K., Laung-Terng Wang, Abdel-Hafez, K.S., Kinoshita, K.

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  16. 16
    An accurate flip-flop selection technique for reducing logic SER

    An accurate flip-flop selection technique for reducing logic SER by Hill, E.L., Lipasti, M.H., Saluja, K.K.

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  17. 17
    Moments Based Blind Calibration in Mobile Sensor Networks

    Moments Based Blind Calibration in Mobile Sensor Networks by Chao Wang, Ramanathan, P., Saluja, K.K.

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  18. 18
    Progressive random access scan: a simultaneous solution to test power, test data volume and test time

    Progressive random access scan: a simultaneous solution to test power, test data volume and test time by Dong Hyun Baik, Saluja, K.K.

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  19. 19
    Testing Flash Memories for Tunnel Oxide Defects

    Testing Flash Memories for Tunnel Oxide Defects by Mohammad, M.G., Saluja, K.K.

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  20. 20
    NBTI Degradation: A Problem or a Scare?

    NBTI Degradation: A Problem or a Scare? by Saluja, K.K., Vijayakumar, S., Sootkaneung, W., Xaingning Yang

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