Search Results - Saluja, Kewal K.

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  1. 1
    Power and Thermal Constrained Test Scheduling Under Deep Submicron Technologies

    Power and Thermal Constrained Test Scheduling Under Deep Submicron Technologies by Chunhua Yao, Saluja, K K, Ramanathan, P

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  2. 2
    Fault Tolerant Lanczos Eigensolver via an Invariant Checking Method

    Fault Tolerant Lanczos Eigensolver via an Invariant Checking Method by Loh, Felix, Saluja, Kewal K., Ramanathan, Parameswaran

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  3. 3
    Fault Tolerance through Invariant Checking for the Lanczos Eigensolver

    Fault Tolerance through Invariant Checking for the Lanczos Eigensolver by Loh, Felix, Saluja, Kewal K., Ramanathan, Parameswaran

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  4. 4
    A Reliability-Aware Methodology to Isolate Timing-Critical Paths under Aging

    A Reliability-Aware Methodology to Isolate Timing-Critical Paths under Aging by Srivastava, Ankush, Singh, Virendra, Singh, Adit D., Saluja, Kewal K.

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  5. 5
    Fault Tolerance through Invariant Checking for Iterative Solvers

    Fault Tolerance through Invariant Checking for Iterative Solvers by Loh, Felix, Saluja, Kewal K., Ramanathan, Parameswaran

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  6. 6
    Adaptive cost efficient deployment strategy for homogeneous wireless camera sensors

    Adaptive cost efficient deployment strategy for homogeneous wireless camera sensors by Lin, Yen-Ting, Saluja, Kewal K., Megerian, Seapahn

    Published in Ad hoc networks
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  7. 7
    Sensor Deployment Strategy for Detection of Targets Traversing a Region

    Sensor Deployment Strategy for Detection of Targets Traversing a Region by Clouqueur, Thomas, Phipatanasuphorn, Veradej, Ramanathan, Parameswaran, Saluja, Kewal K

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  8. 8
    Temperature Minimization Using Power Redistribution in Embedded Systems

    Temperature Minimization Using Power Redistribution in Embedded Systems by Ahmed, Rehan, Ramanathan, Parameswaran, Saluja, Kewal K.

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  9. 9
    Optimal Test Scheduling Formulation under Power Constraints with Dynamic Voltage and Frequency Scaling

    Optimal Test Scheduling Formulation under Power Constraints with Dynamic Voltage and Frequency Scaling by Millican, Spencer K., Saluja, Kewal K.

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  10. 10
    A Test Partitioning Technique for Scheduling Tests for Thermally Constrained 3D Integrated Circuits

    A Test Partitioning Technique for Scheduling Tests for Thermally Constrained 3D Integrated Circuits by Millican, Spencer K., Saluja, Kewal K.

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  11. 11
    Calibrating On-chip Thermal Sensors in Integrated Circuits: A Design-for-Calibration Approach

    Calibrating On-chip Thermal Sensors in Integrated Circuits: A Design-for-Calibration Approach by Yao, Chunhua, Saluja, Kewal K., Ramanathan, Parmesh

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  12. 12
    A Methodology for Identifying High Timing Variability Paths in Complex Designs

    A Methodology for Identifying High Timing Variability Paths in Complex Designs by Srivastava, Ankush, Singh, Virendra, Singh, Adit D., Saluja, Kewal K.

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  13. 13
    Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing

    Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing by Wen, Xiaoqing, Miyase, Kohei, Suzuki, Tatsuya, Kajihara, Seiji, Wang, Laung-Terng, Saluja, Kewal K., Kinoshita, Kozo

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  14. 14
    Instruction-Based Self-Testing of Delay Faults in Pipelined Processors

    Instruction-Based Self-Testing of Delay Faults in Pipelined Processors by Singh, V., Inoue, M., Saluja, K.K., Fujiwara, H.

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  15. 15
    Scheduling tests for VLSI systems under power constraints

    Scheduling tests for VLSI systems under power constraints by Chou, R.M., Saluja, K.K., Agrawal, V.D.

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  16. 16
    Analysis and test procedures for NOR flash memory defects

    Analysis and test procedures for NOR flash memory defects by Mohammad, Mohammad Gh, Saluja, Kewal K.

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  17. 17
    Modeling Detection Latency with Collaborative Mobile Sensing Architecture

    Modeling Detection Latency with Collaborative Mobile Sensing Architecture by Tai-Lin Chin, Ramanathan, P., Saluja, K.K.

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  18. 18
    Low-Area Wrapper Cell Design for Hierarchical SoC Testing

    Low-Area Wrapper Cell Design for Hierarchical SoC Testing by Kim, Kyuchull, Saluja, Kewal K.

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  19. 19
    Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations

    Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations by Lin Xie, Davoodi, Azadeh, Saluja, Kewal K

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  20. 20
    Necessary and Sufficient Conditions for Thermal Schedulability of Periodic Real-Time Tasks Under Fluid Scheduling Model

    Necessary and Sufficient Conditions for Thermal Schedulability of Periodic Real-Time Tasks Under Fluid Scheduling Model by Ahmed, Rehan, Ramanathan, Parameswaran, Saluja, Kewal K.

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