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Search Results - Sang-Hyeok Chu
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A Programmable On-Chip Reference Oscillator With Slow-Wave Coplanar Waveguide in 14-nm FinFET CMOS
by
Hwang, Jeongho
,
Chu, Sang-Hyeok
,
Jeong, Gyu-Seob
,
Youn, Yeojoon
,
Kim, Wooseok
,
Kim, Taeik
,
Jeong, Deog-Kyoon
Published in
IEEE transactions on circuits and systems. II, Express briefs
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A 22 to 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in a 65 nm CMOS Process
by
Chu, Sang-Hyeok
,
Bae, Woorham
,
Jeong, Gyu-Seob
,
Jang, Sungchun
,
Kim, Sungwoo
,
Joo, Jiho
,
Kim, Gyungock
,
Jeong, Deog-Kyoon
Published in
IEEE journal of solid-state circuits
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An Optimum Loop Gain Tracking All-Digital PLL Using Autocorrelation of Bang-Bang Phase-Frequency Detection
by
Jang, Sungchun
,
Kim, Sungwoo
,
Chu, Sang-Hyeok
,
Jeong, Gyu-Seob
,
Kim, Yoonsoo
,
Jeong, Deog-Kyoon
Published in
IEEE transactions on circuits and systems. II, Express briefs
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A 55.1 mW 1.62-to-8.1 Gb/s Video Interface Receiver Generating up to 680 MHz Stream Clock Over 20 dB Loss Channel
by
Park, Kwanseo
,
Lee, Jinhyung
,
Lee, Kwangho
,
Choo, Min-Seong
,
Jang, Sungchun
,
Chu, Sang-Hyeok
,
Kim, Sungwoo
,
Jeong, Deog-Kyoon
Published in
IEEE transactions on circuits and systems. II, Express briefs
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A 20 Gb/s 0.4 pJ/b Energy-Efficient Transmitter Driver Utilizing Constant- Bias
by
Gyu-Seob Jeong
,
Sang-Hyeok Chu
,
Yoonsoo Kim
,
Sungchun Jang
,
Sungwoo Kim
,
Woorham Bae
,
Sung-Yong Cho
,
Ju, Haram
,
Deog-Kyoon Jeong
Published in
IEEE journal of solid-state circuits
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A Four-Channel 32-Gb/s Transceiver With Current-Recycling Output Driver and On-Chip AC Coupling in 65-nm CMOS Process
by
Kim, Taeho
,
Jang, Sungchun
,
Kim, Sungwoo
,
Chu, Sang-Hyeok
,
Park, Jiheon
,
Jeong, Deog-Kyoon
Published in
IEEE transactions on circuits and systems. II, Express briefs
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A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection
by
Sung-Yong Cho
,
Sungwoo Kim
,
Min-Seong Choo
,
Jinhyung Lee
,
Han-Gon Ko
,
Sungchun Jang
,
Sang-Hyeok Chu
,
Bae, Woorham
,
Yoonsoo Kim
,
Deog-Kyoon Jeong
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An all-digital bang-bang PLL using two-point modulation and background gain calibration for spread spectrum clock generation
by
Jang, Sungchun
,
Kim, Sungwoo
,
Chu, Sang-Hyeok
,
Jeong, Gyu-Seob
,
Kim, Yoonsoo
,
Jeong, Deog-Kyoon
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6.4 A 56Gb/s 7.7mW/Gb/s PAM-4 Wireline Transceiver in 10nm FinFET Using MM-CDR-Based ADC Timing Skew Control and Low-Power DSP with Approximate Multiplier
by
Yoo, Byoung-Joo
,
Lim, Dong-Hyuk
,
Pang, Hyonguk
,
Lee, June-Hee
,
Baek, Seung-Yeob
,
Kim, Naxin
,
Choi, Dong-Ho
,
Choi, Young-Ho
,
Yang, Hyeyeon
,
Yoon, Taehun
,
Chu, Sang-Hyeok
,
Kim, Kangjik
,
Jung, Woochul
,
Kim, Bong-Kyu
,
Lee, Jaechol
,
Kang, Gunil
,
Park, Sang-Hune
,
Choi, Michael
,
Shin, Jongshin
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