2D cache architecture for motion compensation in a 4K Ultra-HD AVC and HEVC video codec system by Sanghvi, Hetul

Request full text

Novel Census Transform Hardware IP by Reghunath, Anish, Mody, Mihir, Sanghvi, Hetul, Ankur

Request full text

An area-efficient 6T-SRAM based Compute-In-Memory architecture with reconfigurable SAR ADCs for energy-efficient deep neural networks in edge ML applications by Biswas, Avishek, Sanghvi, Hetul, Mehendale, Mahesh, Preet, G

Request full text

Flexible Wide Dynamic Range (WDR) processing support in image signal processor (ISP) by Mody, Mihir, Nandan, Niraj, Allu, Hetul Sanghvi Rajasekhar, Sagar, Rajat

Request full text

2.6 A 16nm 3.5B+ Transistor >14TOPS 2-to-10W Multicore SoC Platform for Automotive and Embedded Applications with Integrated Safety MCU, 512b Vector VLIW DSP, Embedded Vision and I... by Venkatasubramanian, Rama, Steiss, Don, Shurtz, Greg, Anderson, Tim, Chirca, Kai, Santhanagopal, Raghavendra, Nandan, Niraj, Reghunath, Anish, Sanghvi, Hetul, Wu, Daniel, Chachad, Abhijeet, Karguth, Brian, Beaudoin, Denis, Fuoco, Charles, Nardini, Lewis, Hu, Chunhua, Visalli, Sam, Mundra, Amrit, Varadarajan, Devanathan, Cano, Frank, Stelmach, Shane, Mody, Mihir, Redfern, Arthur, Bilhan, Haydar, Sarraj, Maher, Siddiki, Ali, Lell, Anthony, Falik, Eldad, Hill, Anthony, Armstrong, Abhinay, Beck, Todd, Kanumuri, Vijay, Mullinnix, Steve, Moore, Darnell, Jones, Jason, Koul, Manoj, Agarwala, Sanjive

Request full text

A 28nm programmable and low power ultra-HD video codec engine by Sanghvi, Hetul, Mody, Mihir, Nandan, Niraj, Mehendale, Mahesh, Das, Subrangshu, Mandal, Dipan Kumar, Shastry, Pavan

Request full text

Accelerating H.264/HEVC video slice processing using application specific instruction set processor by Mandal, Dipan Kumar, Mody, Mihir, Mehendale, Mahesh, Yadav, Naresh, Chaitanya, Ghone, Goswami, Piyali, Sanghvi, Hetul, Nandan, Niraj

Request full text

A monolithic programmable Ultra-HD video codec engine by Sanghvi, Hetul, Mody, Mihir, Nandan, Niraj, Mehendale, Mahesh, Das, Subrangshu, Mandal, Dipan Kumar, Nainala, Vyagrheswarudu, Baireddy, Vijayavardhan, Shastry, Pavan

Request full text

Efficient VLSI architecture for SAO decoding in 4K Ultra-HD HEVC video codec by Mody, Mihir, Nandan, Niraj, Sanghvi, Hetul

Request full text

Generic transfer scheme for outputting video frame in Ultra-HD video Engine by Mody, Mihir, Nandan, Niraj, Sanghvi, Hetul

Request full text

Low power architecture for motion compensation filter in a 4K Ultra HD video codec accelerator by Sanghvi, Hetul, Nandan, Niraj, Mody, Mihir

Request full text

Motion vector dependent filter strength computation for high performance H.264 de-blocking loop filter by Nandan, Niraj, Mody, Mihir, Sanghvi, Hetul

Request full text

DBQ: A Differentiable Branch Quantizer for Lightweight Deep Neural Networks by Dbouk, Hassan, Sanghvi, Hetul, Mehendale, Mahesh, Shanbhag, Naresh

Get full text

Customization of de-blocking filter edge order for high performance: Study of H.264 AVC/SVC, H.265 by Nandan, Niraj, Mody, Mihir, Sanghvi, Hetul, Shankar, Prithvi

Request full text

A 216 GOPS flexible WDR Image Processor for ADAS SoC by Mody, Mihir, Sanghvi, Hetul, Nandan, Niraj, Dabral, Shashank, Allu, Rajasekhar, Sagar, Rajat, Chitnis, Kedar, Jones, Jason, Jadhav, Brijesh, Shivalingappa, Sujith, Dubey, Aish

Request full text

High performance and flexible imaging Sub-system by Mody, Mihir, Sanghvi, Hetul, Nandan, Niraj, Dabral, Shashank, Allu, Rajasekhar, Soni, Dharmendra, Sah, Sunil, Seshadri, Gayathri, Karandikar, Prashant

Request full text

Efficient system level cache architecture for multimedia SoC by Karandikar, Prashant, Mody, Mihir, Sanghvi, Hetul, Easwaran, Vasant, Prithvi, Shankar Y. A., Gulati, Rahul, Nandan, Niraj, Das, Subrangshu

Request full text

Understanding system level caching behavior in multimedia SoC by Karandikar, Prashant, Mody, Mihir, Sanghvi, Hetul, Easwaran, Vasant, Prithvi Shankar, Y. A., Gulati, Rahul, Nandan, Neeraj, Mandal, Dipan, Das, Subrangshu

Request full text