Search Results - Sass, A. R.

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  1. 1
    Impressions of Disadvantage: I. School versus University Study Orchestration and Consequences for Academic Support

    Impressions of Disadvantage: I. School versus University Study Orchestration and Consequences for Academic Support by Meyer, J. H. F., Dunne, T. T., Sass, A. R.

    Published in Higher education
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  2. 2
    Designing Modular Hardware Accelerators in C with ROCCC 2.0

    Designing Modular Hardware Accelerators in C with ROCCC 2.0 by Villarreal, Jason, Park, Adrian, Najjar, Walid, Halstead, Robert

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  3. 3
    Odin II - An Open-Source Verilog HDL Synthesis Tool for CAD Research

    Odin II - An Open-Source Verilog HDL Synthesis Tool for CAD Research by Jamieson, Peter, Kent, Kenneth B, Gharibian, Farnaz, Shannon, Lesley

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  4. 4
    Image Properties of a Superconducting Ground Plane

    Image Properties of a Superconducting Ground Plane by Sass, A. R.

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  5. 5
    Superconducting-to-Normally Conducting Transitions in Strip Transmission Line Structures

    Superconducting-to-Normally Conducting Transitions in Strip Transmission Line Structures by Sass, A. R., Friedlaender, F. J.

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  6. 6
    Self and Mutual Inductances of Superconducting Structures

    Self and Mutual Inductances of Superconducting Structures by Sass, A. R., Stewart, W. C.

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  7. 7
    Accelerating Viola-Jones Face Detection to FPGA-Level Using GPUs

    Accelerating Viola-Jones Face Detection to FPGA-Level Using GPUs by Hefenbrock, Daniel, Oberg, Jason, Nhat Thanh, Kastner, Ryan, Baden, Scott B

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  8. 8
    Current Distribution in a Thin-Film Superconducting Strip Transmission Line

    Current Distribution in a Thin-Film Superconducting Strip Transmission Line by Sass, A. R., Skurnick, I. D.

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  9. 9
    Fast and Efficient FPGA-Based Feature Detection Employing the SURF Algorithm

    Fast and Efficient FPGA-Based Feature Detection Employing the SURF Algorithm by Bouris, Dimitris, Nikitakis, Antonis, Papaefstathiou, Ioannis

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  10. 10
    A Large-Scale Architecture for Restricted Boltzmann Machines

    A Large-Scale Architecture for Restricted Boltzmann Machines by Sang Kyun Kim, McMahon, Peter L, Olukotun, Kunle

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  11. 11
    Impulse C vs. VHDL for Accelerating Tomographic Reconstruction

    Impulse C vs. VHDL for Accelerating Tomographic Reconstruction by Xu, Jimmy, Subramanian, Nikhil, Alessio, Adam, Hauck, Scott

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  12. 12
    Crossed-film cryotron switching speed

    Crossed-film cryotron switching speed by Sass, A., Stewart, W., Dworsky, L., Hoffstein, V., Schein, L.

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  13. 13
    Improving the Robustness of a Softcore Processor against SEUs by Using TMR and Partial Reconfiguration

    Improving the Robustness of a Softcore Processor against SEUs by Using TMR and Partial Reconfiguration by Ichinomiya, Yoshihiro, Tanoue, Shiro, Amagasaki, Motoki, Iida, Masahiro, Kuga, Morihiro, Sueyoshi, Toshinori

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  14. 14
    SIRC: An Extensible Reconfigurable Computing Communication API

    SIRC: An Extensible Reconfigurable Computing Communication API by Eguro, Ken

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  15. 15
    Cryogenic random-access memories

    Cryogenic random-access memories by Sass, A. R., Stewart, W. C., Cosentino, L. S.

    Published in IEEE spectrum
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  16. 16
    Using the Power Side Channel of FPGAs for Communication

    Using the Power Side Channel of FPGAs for Communication by Ziener, Daniel, Baueregger, Florian, Teich, Jürgen

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  17. 17
    A Design Methodology for Application Partitioning and Architecture Development of Reconfigurable Multiprocessor Systems-on-Chip

    A Design Methodology for Application Partitioning and Architecture Development of Reconfigurable Multiprocessor Systems-on-Chip by Göhringer, Diana, Hübner, Michael, Benz, Michael, Becker, Jürgen

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  18. 18
    DPA Resistant AES on FPGA Using Partial DDL

    DPA Resistant AES on FPGA Using Partial DDL by Kaps, Jens-Peter, Velegalati, Rajesh

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  19. 19
    Energy-Aware Optimisation for Run-Time Reconfiguration

    Energy-Aware Optimisation for Run-Time Reconfiguration by Becker, Tobias, Luk, Wayne, Cheung, Peter Y K

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  20. 20
    A Heterogeneous FPGA Architecture for Support Vector Machine Training

    A Heterogeneous FPGA Architecture for Support Vector Machine Training by Papadonikolakis, Markos, Bouganis, Christos-Savvas

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