Improving accuracy, robustness and computational efficiency in 3D computer vision by Crossley, S., Seed, N.L., Thacker, N.A., Ivey, P.A.

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Continuous and high coverage self-testing of dynamically re-configurable systems by Zawada, A.C., Seed, N.L., Ivey, P.A.

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Animate vision demonstrator utilising reconfigurable system designs by Shelley, A.J, Seed, N.L

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Photolithography on Grossly Non-Planar Substrates by Williams, G.L., McWilliam, R., Maiden, A., Purvis, A., Ivey, P.A., Seed, N.L.

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HART, a heterogeneous architecture for real-time prototyping, development and implementation of machine vision applications by Goodenough, J., Shelley, A.J., Seed, N.L.

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Using the cluster-based location routing (CBLR) algorithm for exchanging information on a motorway by Santos, R.A., Edwards, R.M., Seed, N.L.

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An ultra compact, low-cost, complete image-processing system by Stem, J.M., Ivey, P.A., Larcombe, S.P., Goodenough, N.J., Seed, N.L., Shelley, A.J.

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A general purpose, single chip video signal processing (VSP) architecture for image processing, coding and computer vision by Goodenough, J., Meacham, R.J., Morris, J.D., Seed, N.L., Ivey, P.A.

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A micro-packaged image acquisition and processing module by Larcombe, S.P, Stern, J.M, Ivey, P.A, Seed, N.L, Shelley, A.J

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A low cost, intelligent micro-camera for surveillance by Larcombe, S.P, Stern, J.M, Ivey, P.A, Seed, N.L

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A computer architecture for real time image processing using VLSI by Houghton, A.D, Seed, N.L

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Digital pulse interval modulation for optical communications by Ghassemlooy, Z., Hayes, A.R., Seed, N.L., Kaluarachchi, E.D.

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