Dynamically tuning processor resources with adaptive processing by Albonesi, D. H., Balasubramonian, R., Dropsbo, S. G., Dwarkadas, S., Friedman, E. G., Huang, M. C., Kursun, V., Magklis, G., Scott, M. L., Semeraro, G., Bose, P., Buyuktosunoglu, A., Cook, P. W., Schuster, S. E.

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Dynamic frequency and voltage scaling for a multiple-clock-domain microprocessor by Magklis, G., Semeraro, G., Albonesi, D.H., Dropsho, S.G., Dwarkadas, S., Scott, M.L.

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Dynamic frequency and voltage control for a multiple clock domain microarchitecture by Semeraro, G., Albonesi, D.H., Dropsho, S.G., Magklis, G., Dwarkadas, S., Scott, M.L.

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Hiding synchronization delays in a GALS processor microarchitecture by Semeraro, G., Albonesi, D.H., Magklis, G., Scott, M.L., Dropsho, S.G., Dwarkadas, S.

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Dynamically Trading Frequency for Complexity in a GALS Microprocessor by Dropsho, Steven, Semeraro, Greg, Albonesi, David H., Magklis, Grigorios, Scott, Michael L.

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Dynamic frequency and voltage control for a multiple clock domain microarchitecture by Semeraro, Greg, Albonesi, David H., Dropsho, Steven G., Magklis, Grigorios, Dwarkadas, Sandhya, Scott, Michael L.

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Profile-based dynamic voltage and frequency scaling for a multiple clock domain microprocessor by Magklis, Grigorios, Scott, Michael L., Semeraro, Greg, Albonesi, David H., Dropsho, Steven

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Dynamically Trading Frequency for Complexity in a GALS Microprocessor by Dropsho, Steven, Semeraro, Greg, Albonesi, David H, Magklis, Grigorios, Scott, Michael L

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Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power by Dropsho, Steve, Buyuktosunoglu, Alper, Balasubramonian, Rajeev, Albonesi, David H., Dwarkadas, Sandhya, Semeraro, Greg, Magklis, Grigorios, Scott, Michael L.

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